38.7.25 Device Endpoint Interrupt Enable Register (Control, Bulk, Interrupt Endpoints)

This register view is relevant only if EPTYPE = 0x0, 0x2, or 0x3 in ”Device Endpoint x Configuration Register”.

For additional information, see ”Device Endpoint x Mask Register (Control, Bulk, Interrupt Endpoints)”.

This register always reads as zero.

The following configuration values are valid for all listed bit names of this register:

0: No effect.

1: Sets the corresponding bit in USBHS_DEVEPTIMRx.

Name:	USBHS_DEVEPTIERx
Offset:	0x01F0 + x*0x04 [x=0..8]
Reset:	0
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
					STALLRQS	RSTDTS	NYETDISS	EPDISHDMAS
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	15	14	13	12	11	10	9	8
		FIFOCONS	KILLBKS	NBUSYBKES
Access		R/W	R/W	R/W
Reset		0	0	0


Bit	7	6	5	4	3	2	1	0
	SHORTPACKETES	STALLEDES	OVERFES	NAKINES	NAKOUTES	RXSTPES	RXOUTES	TXINES
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 19 – STALLRQS STALL Request Enable

Bit 18 – RSTDTS Reset Data Toggle Enable

Bit 17 – NYETDISS NYET Token Disable Enable

Bit 16 – EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable

Bit 14 – FIFOCONS FIFO Control

Bit 13 – KILLBKS Kill IN Bank

Bit 12 – NBUSYBKES Number of Busy Banks Interrupt Enable

Bit 7 – SHORTPACKETES Short Packet Interrupt Enable

Bit 6 – STALLEDES STALLed Interrupt Enable

Bit 5 – OVERFES Overflow Interrupt Enable

Bit 4 – NAKINES NAKed IN Interrupt Enable

Bit 3 – NAKOUTES NAKed OUT Interrupt Enable

Bit 2 – RXSTPES Received SETUP Interrupt Enable

Bit 1 – RXOUTES Received OUT Data Interrupt Enable

Bit 0 – TXINES Transmitted IN Data Interrupt Enable

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