18.2.3.1.3 64-Bit and 32-Bit Modes

Timers 1 and 2 can be concatenated into a single 64-bit Timer that operates either in Periodic mode or in One-shot mode. Figure 18-3 and Figure 18-4 show block diagrams for 32-bit mode and 64 -bit mode. Writing 1 to the Table 18-20 register bit 0 sets the Timers in 64-bit mode. Whenever the TIM64_MODE bit changes state, the Timers are re-initialized to their default reset values. In 64-bit mode, writing to the 32-bit registers has no effect. Similarly, in 32-bit mode, writing to the 64-bit mode registers has no effect. Reading the 32-bit registers in 64-bit mode returns the default initialization values. Similarly, reading the 64-bit mode registers in 32-bit mode returns the default initialization values.

Timer 1 contains the lower 32-bit count of the 64-bit count value. Consequently, when updating or initializing the state of the counter, the upper 32 bits of the 64-bit counter must be written to first, followed by the lower 32 bits. It occurs as a two step process, first the upper 32 bits are written and then this value is stored in temporary register. When you write the lower 32 bits, the upper 32 bits are simultaneously written to the destination register. If a read is done on the target register before the write to the lower 
32 bits is done, the functional value of the target register is returned (not the value of the temporary register).

While updating the background load value registers, ensure that TIM64_BGLOAD_VAL_U is followed by a write to TIM64_BGLOADVAL_L. When updating the load value registers, ensure TIM64_LOADVAL_U is followed by a write to TIM64_LOADVAL_L. When the lower 32-bit write occurs, the 64-bit counter is updated as one 64-bit value. There are temporary holding registers in the Timer block that are used to facilitate proper loading of the Timer in 64-bit mode. These registers are not readable.

In 64-bit mode, it is necessary to read 64-bit values as two 32-bit words. While reading TIM64_VAL_U and TIM64VAL_L, TIM64_VAL_L should be read first and then TIM64_VAL_U. When the TIM64_VAL_L (lower 32 bits of the 64-bit word) is read, the upper 32 bits are simultaneously read and put in a temporary register, which is returned while reading TIM64_VAL_U. This assures that the (changing) Timer values of the upper and lower words presented are sampled at the same time. The registers TIM64_BGLOADVAL_U, TIM64_BGLOADVAL_L, TIM64_LOADVAL_U, and TIM64_LOADVAL_L can be read in any order. Switching modes from 32-bit to 64-bit and vice versa requires changing the value in the mode register. Whenever this value is changed, the register values are restarted as the Timer is just reset.

Each 32-bit counter in the Timer is clocked with the PCLK input. With a PCLK frequency of 100 MHz, the maximum timeout period is approximately 42.9 seconds in 32-bit mode and 1.8 × 1011 seconds in 64-bit mode.