14.4.8 Slave1 Address Register
The I2C has dual slave address (Slave0/Slave1) decoding capability. The Slave0 address register is a read/write directly accessible register. The details of this register are provided in the following table.
| Bit Number | Name | R/W | Reset Value | Description |
|---|---|---|---|---|
| 7 | ADR6 | R/W | 0 | Own Slave1 address bit 6 |
| 6 | ADR5 | R/W | 0 | Own Slave1 address bit 5 |
| 5 | ADR4 | R/W | 0 | Own Slave1 address bit 4 |
| 4 | ADR3 | R/W | 0 | Own Slave1 address bit 3 |
| 3 | ADR2 | R/W | 0 | Own Slave1 address bit 2 |
| 2 | ADR1 | R/W | 0 | Own Slave1 address bit 1 |
| 1 | ADR0 | R/W | 0 | Own Slave1 address bit 0 |
| 0 | ENADR | R/W | 0 | 1: Enable the Slave1 address comparisons 0: Disable Slave1 address comparisons |