14.4.4 Slave0 Address Register

The I²C has dual slave address (Slave0/Slave1) decoding capability. The Slave0 address register is a read/write directly accessible register. The details of this register are provided in the following table.

Table 14-14. Slave0 Address Register (Slave0 ADR)
Bit Number	Name	R/W	Description
7	ADR6	R/W	Own Slave0 address bit 6
6	ADR5	R/W	Own Slave0 address bit 5
5	ADR4	R/W	Own Slave0 address bit 4
4	ADR3	R/W	Own Slave0 address bit 3
3	ADR2	R/W	Own Slave0 address bit 2
2	ADR1	R/W	Own Slave0 address bit 1
1	ADR0	R/W	Own Slave0 address bit 0
0	GC	R/W	General call (GC) address acknowledge. If the GC bit is set, the general call address is recognized; otherwise it is ignored.