14.4.3 Data Register
The Data register contains a byte of serial data to be transmitted or a byte that is received. The Cortex-M3 processor or any other fabric master can read from and write to this 8-bit, directly addressable register when it is not shifting a byte (after an interrupt is generated).
The bit descriptions are provided in the following table, in both data and addressing context. Data context is the 8-bit data format from MSB to LSB. Addressing context is based on a master sending an address call to a slave on the bus, along with a direction bit (master transmits data or receives data from a slave).
| Bit Number | Name | R/W | Reset Value | Description |
|---|---|---|---|---|
| 7 | SD7 | R/W | 0 | Data context: serial data bit 7(MSB) Addressing context: serial address bit 6(MSB) |
| 6 | SD6 | R/W | 0 | Data context: serial data bit 6 Addressing context: serial address bit 5 |
| 5 | SD5 | R/W | 0 | Data context: serial data bit 5 Addressing context: serial address bit 4 |
| 4 | SD4 | R/W | 0 | Data context: serial data bit 4 Addressing context: serial address bit 3 |
| 3 | SD3 | R/W | 0 | Data context: serial data bit 3 Addressing context: serial address bit 2 |
| 2 | SD2 | R/W | 0 | Data context: serial data bit 2 Addressing context: serial address bit 1 |
| 1 | SD1 | R/W | 0 | Data context: serial data bit 1 Addressing context: serial address bit 0 (LSB) |
| 0 | SD0 | R/W | 0 | Data context: serial data bit 0 (LSB) Addressing context: direction bit. 0 = Write; 1 = Read |