19.2.1.3 Timeout Detection

A control bit in the WDOGCONTROL register is used to determine whether the watchdog timer generates a reset or an interrupt if a counter timeout occurs. The default setting is reset generation on timeout. When interrupt generation is selected, the WDOGTIMEOUTINT output is asserted on timeout and remains asserted until the interrupt is cleared. When reset generation is selected, the watchdog timer does not directly generate the system reset signal. Instead, when the counter reaches zero, the watchdog timer generates a pulse on the WDOGTIMEOUT output and this is routed to the reset controller to cause it to assert the necessary reset signals. The pulse on the WDOGTIMEOUT output is generated in the RCOSCCLK domain and has duration of one clock cycle.