19.2.1.2 32-Bit Counter

The operation of the watchdog timer is based on a 32-bit down counter that must be refreshed at regular intervals by the Cortex-M3 processor. If not refreshed, the counter will time out. This either causes a system reset or generates an interrupt to the processor, depending on the value of the WDOGMODE bit as defined in the WDOG_CR Register.

The WDOG_CR register is one of the system registers that helps to configure the watchdog timer. In normal operation, the generation of a reset or timeout interrupt by the watchdog timer does not occur because the watchdog timer counter is refreshed on a regular basis.

When the device is powered up, the watchdog timer is enabled with the timeout period set to approximately 10.47 seconds (if Vdd = 1.2 V). The WDOGENABLE bit in the WDOG_CR register controls enabling/disabling of the watchdog timer.

The memory map address for the watchdog timer is 0x40005000-0x40005FFF. The 32-bit counter in the watchdog timer is clocked with the clock signal from the RC Oscillator (RCOSCCLK) which has a frequency of 50 MHz (if Vdd = 1.2 V) with a 5% tolerance.