15.4.6 GPIO System Reset Control Register

Table 15-10. GPIO_SYSRESET_SEL_CR
Bit Number Name Reset Value Description
[31:4] Reserved 0 Reserved
3 MSS_GPIO_31_24_SYSRESET_SEL 0 0: The GPIO[31:24] is reset by either power-on reset or the MSS_GPIO_RESET_N signal from the FPGA fabric.

1: The GPIO[31:24] is reset by the soft reset signal MSS_GPIO_31_24_SOFT_RESET.
2 MSS_GPIO_23_16_SYSRESET_SEL 0 0: The GPIO[23:16] is reset by either power-on reset or the MSS_GPIO_RESET_N signal from the FPGA fabric.

1: The GPIO[23:16] is reset by the soft reset signal MSS_GPIO_23_16_SOFT_RESET.
1 MSS_GPIO_15_8_SYSRESET_SEL 0 0: The GPIO[15:8] is reset by either power-on reset or the MSS_GPIO_RESET_N signal from the FPGA fabric.

1: The GPIO[15:8] is reset by the soft reset signal MSS_GPIO_15_8_SOFT_RESET.
0 MSS_GPIO_7_0_SYSRESET_SEL 0 0: The GPIO[7:0] is reset by either power-on reset or the MSS_GPIO_RESET_N signal from the FPGA fabric.

1: The GPIO[7:0] is reset by the soft reset signal MSS_GPIO_7_0_SOFT_RESET.