15.4.2 Software Reset Control Register

Table 15-6. SOFT_RESET_CR
Bit Number	Name	Reset Value	Description
24	MSS_GPOUT_31_24_SOFTRESET	0x1	0: Releases GPIO_OUT[31:24] from reset 1: Keeps GPIO_OUT[31:24] in reset
23	MSS_GPOUT_23_16_SOFTRESET	0x1	0: Releases GPIO_OUT[23:16] from reset 1: Keeps GPIO_OUT[23:16] in reset
22	MSS_GPOUT_15_8_SOFTRESET	0x1	0: Releases GPIO_OUT[15:8] from reset 1: Keeps GPIO_OUT[15:8] in reset
21	MSS_GPOUT_7_0_SOFTRESET	0x1	0: Releases GPIO_OUT[7:0] from reset 1: Keeps GPIO_OUT[7:0] in reset
20	MSS_GPIO_SOFTRESET	0x1	0: Releases the GPIO from reset, if not being held in reset by some other means 1: Keeps the GPIO held in reset Asserting this soft reset bit will hold the APB register, GPIO input, and interrupt generation logic in reset. GPIO OUT logic is not affected by this reset.

24

MSS_GPOUT_31_24_SOFTRESET

0x1

0: Releases GPIO_OUT[31:24] from reset 1: Keeps GPIO_OUT[31:24] in reset

23

MSS_GPOUT_23_16_SOFTRESET

0x1

0: Releases GPIO_OUT[23:16] from reset 1: Keeps GPIO_OUT[23:16] in reset

22

MSS_GPOUT_15_8_SOFTRESET

0x1

0: Releases GPIO_OUT[15:8] from reset 1: Keeps GPIO_OUT[15:8] in reset

21

MSS_GPOUT_7_0_SOFTRESET

0x1

0: Releases GPIO_OUT[7:0] from reset 1: Keeps GPIO_OUT[7:0] in reset

20

MSS_GPIO_SOFTRESET

0x1

0: Releases the GPIO from reset, if not being held in reset by some other means

1: Keeps the GPIO held in reset

Asserting this soft reset bit will hold the APB register, GPIO input, and interrupt generation logic in reset. GPIO OUT logic is not affected by this reset.