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SmartFusion 2 Microcontroller Subsystem
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15
MSS GPIO
15.4
GPIO Register Map
15.4.1
SYSREG Block Registers
Introduction
1
Cortex-M3 Processor Overview and Debug Features
2
Cortex-M3 Processor (Reference Material)
3
Cache Controller
4
Embedded NVM (eNVM) Controllers
5
Embedded SRAM (eSRAM) Controllers
6
AHB Bus Matrix
7
High Performance DMA Controller
8
Peripheral DMA
9
Universal Serial Bus On-The-Go Controller
10
Ethernet MAC
11
CAN Controller
12
MMUART Peripherals
13
Serial Peripheral Interface Controller
14
Inter-Integrated Circuit Peripherals
15
MSS GPIO
15.1
Features
15.2
MSS GPIO Functional Description
15.3
MSS GPIO Usage
15.4
GPIO Register Map
15.4.1
SYSREG Block Registers
15.4.1.1
Register Map
15.4.2
Software Reset Control Register
15.4.3
MSS GPIO Definitions
15.4.4
Loopback Control Register
15.4.5
GPIO Input Source Select Control Register
15.4.6
GPIO System Reset Control Register
15.4.7
I/O MUX Associated With GPIOs
16
Communication Block
17
RTC System
18
System Timer
19
Watchdog Timer
20
Reset Controller
21
System Register Block
22
Fabric Interface Interrupt Controller
23
Fabric Interface Controller
24
APB Configuration Interface
25
Error Detection and Correction Controllers
26
Revision History
Microchip FPGA Support
Microchip Information
15.4.1 SYSREG Block Registers
