18.4.5 Timer x Raw Interrupt Status Register
| Bit Number | Name | R/W | Reset Value | Description |
|---|---|---|---|---|
| 31:1 | Reserved | R/W | 0 | Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. |
| 0 | TIMx_RIS | R/W | 0 | Timer x raw interrupt status (RIS) 0: Timer x has not reached zero 1: Timer x has reached zero at least once since this bit was last cleared (by a reset or by writing 1 to this bit). Writing a 1 to this bit clears the bit and the interrupt, writing a zero has no effect. Writing this register when the Timer is set to 64-bit mode has no effect. Reading this register when the Timer is set to 64-bit mode returns the reset value. |