22.3.2.2.1 Software Design Flow
The software design flow consists of enabling the MSS to the fabric interrupts.
Enabling the MSS to the Fabric interrupt
The interrupt enable registers do not affect the Cortex-M3 process or the NVIC; these are per bit enables of the interrupt routed to the FPGA fabric. It enables the MSS to fabric interrupt, MSS_INT_M2F, by setting the following INTERRUPT_ENABLE0 or INTERRUPT_ENABLE1 register bit-band.
INTERRUPT_CTRL_BITBAND-> bit-band register bit of INTERRUPT_ENABLE0 or INTERRUPT_ENABLE1 = <1/0>;
The following table gives the bit-band register bit of INTERRUPT_ENABLE0
and INTERRUPT_ENABLE1 in INTERRUPT_CTRL structure. See m2sxxx.h
contained
in the CMSIS folder.
Bit-Band Register Bit | |
---|---|
INTERRUPT_ENABLE0 | INTERRUPT_ENABLE1 |
SPIINT0_ENBL | RESERVED1[3] |
SPIINT1_ENBL | MDDR_IO_CALIB_INT_ENBL |
I2C_INT0_ENBL | RESERVED2 |
I2C_INT1_ENBL | FAB_PLL_LOCK_INT_ENBL |
MMUART0_INTR_ENBL | FAB_PLL_LOCKLOST_INT_ENBL |
MMUART1_INTR_ENBL | FIC64_INT_ENBL |
MAC_INT_ENBL | RESERVED3[24] |
USB_MC_INT_ENBL | — |
PDMAINTERRUPT_ENBL | — |
HPD_XFR_CMP_INT_ENBL | — |
TIMER1_INTR_ENBL | — |
TIMER2_INTR_ENBL | — |
CAN_INTR_ENBL | — |
RTC_WAKEUP_INTR_ENBL | — |
WDOGWAKEUPINT_ENBL | — |
MSSDDR_PLL_LOCKLOST_INT_ENBL | — |
ENVM_INT0_ENBL | — |
ENVM_INT1_ENBL | — |
I2C_SMBALERT0_ENBL | — |
I2C_SMBSUS0_ENBL | — |
I2C_SMBALERT1_ENBL | — |
I2C_SMBSUS1_ENBL | — |
HPD_XFR_ERR_INT_ENBL | — |
MSSDDR_PLL_LOCK_INT_ENBL | — |
SW_ERRORINTERRUPT_ENBL | — |
DDRB_INTR_ENBL | — |
ECCINTR_ENBL | — |
CACHE_ERRINTR_ENBL | — |
SOFTINTERRUPT_ENBL | — |
COMBLK_INTR_ENBL | — |
USB_DMA_INT_ENBL | — |
RESERVED0 | — |
To enable the MSS to the fabric interrupts, listed in the Select Group 0 or Select Group 1 column of Table 22-1, set the bit-band register bit of INTERRUPT_MODE register as follows:
INTERRUPT_CTRL_BITBAND-> SELECT_MODE= <1/0>;
Monitoring the MSS to the Fabric Interrupt Status
The status of the MSS to the fabric interrupt, MSS_INT_M2F, can be monitored by reading the bit-band register bit of INTERRUPT_REASON0 and INTERRUPT_REASON1, as follows:
INTERRUPT_CTRL_BITBAND-> bit-band register bit of INTERRUPT_REASON0 or INTERRUPT_REASON1;
The following table gives the bit-band register bit of INTERRUPT_REASON0
and INTERRUPT_REASON1 in the INTERRUPT_CTRL structure. Refer to m2sxxx.h
contained in the CMSIS folder.
Bit-Band Register Bit | |
---|---|
INTERRUPT_REASON0 | INTERRUPT_REASON1 |
SPIINT0_STATUS | RESERVED5[3] |
SPIINT1_STATUS | MDDR_IO_CALIB_INT_STATUS |
I2C_INT0_STATUS | RESERVED6 |
I2C_INT1_STATUS | FAB_PLL_LOCK_INT_STATUS |
MMUART0_INTR_STATUS | FAB_PLL_LOCKLOST_INT_STATUS |
MMUART1_INTR_STATUS | FIC64_INT_STATUS |
MAC_INT_STATUS | RESERVED7[24] |
USB_MC_INT_STATUS | |
PDMAINTERRUPT_STATUS | |
HPD_XFR_CMP_INT_STATUS | |
TIMER1_INTR_STATUS | |
TIMER2_INTR_STATUS | |
CAN_INTR_STATUS | |
RTC_WAKEUP_INTR_STATUS | |
WDOGWAKEUPINT_STATUS | |
MSSDDR_PLL_LOCKLOST_INT_STATUS | |
ENVM_INT0_STATUS | |
ENVM_INT1_STATUS | |
I2C_SMBALERT0_STATUS | |
I2C_SMBSUS0_STATUS | |
I2C_SMBALERT1_STATUS | |
I2C_SMBSUS1_STATUS | |
HPD_XFR_ERR_INT_STATUS | |
MSSDDR_PLL_LOCK_INT_STATUS | |
SW_ERRORINTERRUPT_STATUS | |
DDRB_INTR_STATUS | |
ECCINTR_STATUS | |
CACHE_ERRINTR_STATUS | |
SOFTINTERRUPT_STATUS | |
COMBLK_INTR_STATUS | |
USB_DMA_INT_STATUS | |
RESERVED4 |
Example: The following code illustrates the usage of the MSS to the fabric interrupt in conjunction with the Timer1 interrupt.
int main()
{
// STEP 1 - Enable Timer1 MSS to Fabric Interrupt (MSS_INT_M2F[10])
INTERRUPT_CTRL_BITBAND->TIMER1_INTR_ENBL = 1;
// STEP 2 - Configure Timer1 in PERIODIC MODE
MSS_TIM1_init(MSS_TIMER_PERIODIC_MODE );
// STEP 3 - Load count value
MSS_TIM1_load_immediate(10000000 );
// STEP 4 - Start Timer1
MSS_TIM1_start();
// STEP 5 - Enable Timer1 Interrupt and IRQ in NVIC
MSS_TIM1_enable_irq();
// Foreground loop
for(;;)
{
;
}
return 0;
}
/*
* Connect MSS_INT_M2F[10] signal to LED.
* Toggle LED on TIM1 interrupt.
*/
__attribute__((__interrupt__)) void Timer1_IRQHandler( void )
{
uint32_t timer1_interrupt;
// Read Timer1 MSS to Fabric Interrupt status
timer1_interrupt = INTERRUPT_CTRL_BITBAND->TIMER1_INTR_STATUS;
// Delay for extending the Timer1 MSS to fabric Interrupt pulse width
delay(10000);
/* Clear TIM1 interrupt */
MSS_TIM1_clear_irq();
}