5.2.3 Pipeline Modes and WAIT States for Read and Write Operations

When any master on the AHB bus matrix operates at a high frequency greater than 100 MHz, and is accessing eSRAM, an extra clock cycle is needed for transactions. An optional pipeline can be enabled on the Read data bus; this adds a clock cycle to all read operations. The pipeline is enabled in both SECDED-ON and SECDED-OFF modes, by default. When the master on the AHB bus matrix operates at low frequency, less than 100 MHz, the pipeline can be turned Off. For information on pipeline enable/ disable, see Table 5-9.

The actual frequency at which this is possible is specified in the AC characteristics table of 
IGLOO2 and SmartFusion2 Datasheet. When the pipeline is disabled, the number of WAIT states is less, increasing throughput of read operations.

The following table describes the wait states in different operation modes. These values indicate the number of wait states inserted by eSRAM controllers and apply to the reads and writes from masters within the MSS. Accessing eSRAM blocks from the FPGA fabric is performed through the fabric interface controller (FIC) interfaces. The FIC interface supports Bypass mode and Pipeline mode.

In Pipeline mode, the FIC interface adds one extra clock cycle for read and write, so the overall latency for accessing the eSRAM increases.