20.2.4 Power-On Reset

The Reset Controller receives a power-on reset signal, PO_RESET_N, from the System Controller, which is a cold reset signal. Its assertion initializes the SmartFusion 2 device to its default reset state.

PO_RESET_N signal is fed to the system register block (SYSREG). The PO_RESET_DETECT bit of the RESET_SOURCE_CR register (defined in Table 20-4) in the SYSREG block is set or reset depending on the PORESET_N signal.

The PORESET_N signal is a synchronized version of the PO_RESET_N signal on M3_CLK.

The Reset Controller generates different synchronized resets to the MSS and the FPGA fabric on the assertion of PO_RESET_N, as shown in the following figure.

Figure 20-11. Functional Block Diagram of Reset Controller During Power-On Reset

The CC_RESET_N is generated on the assertion of PO_RESET_N. This is a power-on reset signal to the fabric alignment clock controller (FACC).