20.2.3 DEVRST_N Power-Up to Functional Time

This scenario provides power-up to functional time data with respect to DEVRST_N when the FPGA fabric, the FPGA I/O, and an external oscillator are used. The design setup is same as the VDD power-up to functional time, as shown in the following figure.

Important: It is not recommended to assert the DEVRST_N pin during programming (including eNVM), as it corrupts the device configuration. For more information on proper usage of the DEVRST_N pin, 
see the Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs Application Note.

The following figure shows the behavior of different signals when DEVRST_N is asserted and MSS is used with VDD = 1.2V, VDDI = 2.5V, and Tj = 25 °C.

Figure 20-9. DEVRST_N Power-Up to Functional Timing

The following table lists power-up to functional time of M2S005, M2S010, M2S025, M2S050, M2S060, M2S090, and M2S150 devices with MSS clock ranging from 3 MHz to 166 MHz.

Important: The timing numbers shown in the following table are for the worst-case condition.
Table 20-2. DEVRST_N Power-Up to Functional Time
Test CaseStart PointEnd PointDescriptionPower-Up to Functional Time (µs)
005010025050060090150
Case1POWER_ON_ RESET_NOutput available at I/OFabric to output518501527521422419694
Case 2POWER_ON_ RESET_NMSS_RESET_N_ M2FFabric to MSS515497524518417414689
Case 3MSS_RESET_ N_M2FOutput available at I/OMSS to output3.53.53.53.34.84.84.8
Case 4DEVRST_NOutput available at I/ODEVRST_N to output706768715691641635871
Case 5DEVRST_NPOWER_ON_ RESET_NDEVRST_N to fabric234289216213237234219
Case 6DEVRST_NMSS_RESET_N_ M2FDEVRST_N to MSS702765712688636630866
Case 7DEVRST_NDDRIO input buffer weak pullDEVRST_N to input buffer weak pull208202197193216215215
DEVRST_NMSIO input buffer weak pullDEVRST_N to input buffer weak pull208202197193216215215
DEVRST_NMSIOD input buffer weak pullDEVRST_N to input buffer weak pull208202197193216215215

The following figure shows the stages that contribute to DEVRST_N power-up to functional time for SmartFusion 2.

Figure 20-10. DEVRST_N Power-up to Functional Time Flow
Important: All timing numbers in Table 20-1 and Table 20-2 are for worst-case conditions.