20.2.6 Block Resets

The Reset Controller generates block level resets for all modules except the AHB bus matrix, cache controller, fabric interface interrupt controller (FIIC), RTC, and SYSREG. These blocks get reset at Power-on Reset or system reset. The Reset Controller receives block enable bits and soft reset requests (SOFT_RESET_CR bits) for various blocks within the MSS from SYSREG to control the block level reset generation. The Reset Controller also generates four GPIO resets, which reset each bank of GPIO signals, as described in the 20.2.6.5 MSS GPIO Bank Resets Generator.

The following figure shows the block level resets from the Reset Controller along with the source of the resets.