20.2.2 VDD Power-Up to Functional Time

The core supply voltage VDD is connected to the appropriate source, and VDD is monitored by the Power-on Reset circuitry to check if it reaches the minimum threshold value and initiates the system controller to release the device from reset. This scenario provides power-up to functional time data when only the FPGA fabric and the FPGA I/O are used with all supplies ramped up except VDD, which is ramped up at the end. The required Power-on Reset delay is set using the Libero SoC tool.

The design uses a fabric counter that starts to operate when POWER_ON_RESET_N is deasserted. The LSB of the counter output is connected to a latch and given to an output buffer, which is then connected to an input buffer of the fabric using an external loopback. This input is used to stop the counter from incrementing. The counter stops as soon as the counter's LSB bit transitions to logic HIGH. The power-up to functional time is measured from the VDD supply ramp to the transition of the fabric buffer output.

The following figure shows the characterization test design setup used for obtaining the VDD power-up to functional timing values.

Important: In this test design setup, PLL is not used and instead clock for the fabric is directly fed from the RC oscillator. If PLL is used in the design, then the power-up to functional time will get impacted because of the PLL lock assertion time.

Figure 20-6. VDD Power-Up to Functional Time Design Setup

The following figure shows the behavior of different signals when VDD is ramped with a Power-on Reset delay of 1 ms from 0V to its minimum threshold level and MSS is used with VDD = 1.2V, VDDI = 2.5V,  Tj = 25 °C, and Power-on Reset delay setting = 1 ms.

Figure 20-7. VDD Power-up to functional timing diagram

The following table lists power-up to functional time data of M2S005, M2S010, M2S025, M2S050, M2S060, M2S090, and M2S150 devices with MSS clock ranging from 3 MHz to 166 MHz.

Important: The timing numbers shown in the below table is for worst-case condition.

Table 20-1. VDD Power-Up to Functional Time
Test Case	Start Point	End Point	Description	Power-Up to Functional Time (µs)
Test Case	Start Point	End Point	Description	005	010	025	050	060	090	150
Case1	POWER_ON_R ESET_N	Output available at I/O	Fabric to output	647	500	531	483	474	524	647
Case 2	POWER_ON_R ESET_N	MSS_RESET_N_ M2F	Fabric to MSS	644	497	528	480	468	518	641
Case 3	MSS_RESET_N_M2F	Output available at I/O	MSS to output	3.6	3.6	3.6	3.4	4.9	4.8	4.8
Case 4	VDD	Output available at I/O	VDD at its minimum threshold level to output	3096	2975	3012	2959	2869	2992	3225
Case 5	VDD	POWER_ON_ RESET_N	VDD at its minimum threshold level to fabric	2476	2487	2496	2486	2406	2563	2602
Case 6	VDD	MSS_RESET_N_ M2F	VDD at its minimum threshold level to MSS	3093	2972	3008	2956	2864	2987	3220
Case 7	VDD	DDRIO input buffer weak pull	VDD at its minimum threshold level to input buffer weak pull	2500	2487	2509	2475	2507	2519	2617
	VDD	MSIO input buffer weak pull	VDD at its minimum threshold level to input buffer weak pull	2504	2491	2510	2478	2517	2525	2620
	VDD	MSIOD input buffer weak pull	VDD at its minimum threshold level to input buffer weak pull	2479	2468	2493	2458	2486	2499	2595

Important: Time taken for different Power-on Reset delay settings can be calculated using the following equation:  (Test case – 2000 µs) + 2 × Power on Reset Delay setting.

The following figure shows stages that contribute to VDD power-up to functional time for SmartFusion 2.

Figure 20-8. VDD Power-Up to Functional Time Flow

Important: Power-up to functional time depends on Power-on Reset delay setting, 1 MHz oscillator frequency, and period variability. At times, it is approximately equal to twice the Power-on Reset delay setting.