20.2.5 System Reset

The system reset (SYSRESET_N) is generated if any of the following conditions are true:

  • SYS_RESET_REQ is asserted from Cortex-M3 processor. SYS_RESET_REQ from the 
Cortex-M3 processor is controlled by the SYSRESETREQ bit in the Application Interrupt and the Reset Control register located at 0XE000ED0C. For more information, see 2 Cortex-M3 Processor (Reference Material).
  • LOCKUP_N is asserted from Cortex-M3 processor in the LOCKUP state. The processor enters into LOCKUP state, if a Fault occurs when executing the NMI or HardFault handlers.
  • Watchdog timeout event from the Watchdog Timer.
  • SC_MSS_RESET_N is asserted from the System Controller during the start-up sequence after power-up.
  • MSS_RESET_N_F2M is asserted from the FPGA fabric interface.

The following figure shows the generation of SYSRESET_N.

Figure 20-12. SYSRESET_N Generation

The inputs SYS_RESET_REQ_N, LOCKUP_N, WD_TIMEOUT_N, SC_MSS_RESET_N, and MSS_RESET_N_F2M are first synchronized on M3_CLK and then combined. The MSS_RESET_N_F2M signal can be used to reset the MSS, independently of any resets coming from the MSS itself. For example, it may be asserted as a result of an external reset event from an off-chip Reset Controller, using an I/O pad to bring the reset input into the fabric.

The following figure shows the various reset signals to the MSS blocks which are generated from Reset Controller on the assertion of SYSRESET_N. It also shows the reset inputs to the Reset Controller, which cause the generation of SYSRESET_N.

Figure 20-13. Functional Block Diagram of Reset Controller During SYSRESET_N

SYSRESET_N resets all blocks in the MSS. When SYSRESET_N asserts low, the entire Cortex-M3 processor is reset, except for the debug logic that exists in the following blocks:

  • Nested vectored interrupt controller (NVIC)
  • Flash patch and breakpoint (FPB)
  • Data watchpoint and trace (DWT)
  • Instrumentation trace macrocell (ITM)
  • AHB-AP