16.2.3 Clocks

APB Interface, Control and Status block, and SII Interface are clocked by PCLK1 from the APB1 bus. RX FIFO and TX FIFO are clocked by data clock (50 MHz RC oscillator). PCLK is derived from the fabric aligned clock controller (FACC) output. See UG0449: SmartFusion2 and IGLOO2 Clocking Resources User Guide.