16.2.5 Interrupts

There is one interrupt signal from the COMM_BLK peripheral. The COMBLK_INTR/COMMS_INT signal is mapped to INTISR[19] in the Cortex-M3 processor Nested Vectored Interrupt Controller (NVIC) and also goes to the FPGA fabric through the FIIC. The interrupt in the COMM_BLK peripheral must be enabled by setting the appropriate bits in the interrupt enable register. Clear the appropriate bit in the 16.5.3 Interrupt Enable Register when servicing the COMMS_INT to prevent a reassertion of the interrupt.