16.2.1 Architecture Overview

The COMM_BLK consists of an APB interface, 8 byte transmit FIFO, and 8 byte receive FIFO. There is one COMM_BLK instantiated in the MSS and one in the system controller; each can communicate with the other. Whenever the Cortex-M3 processor writes a character into the COMM_BLK, it is transmitted to the receiving side of the COMM_BLK and an interrupt is asserted to the system controller.

In the other direction, the interrupt (COMM_BLK_INT) goes to both the Cortex-M3 processor and the FPGA fabric through the Fabric Interface Interrupt Controller (FIIC). This communication link is used as a message passing mailbox by firmware running on the Cortex-M3 processor and system controller. The following figure shows how COMM_BLKs are connected to create a communication channel between the Cortex-M3 processor and the system controller.

The COMM_BLK supports PDMA operation. The peripheral ready signals, RxRDY and TxRDY are directly connected to the PDMA, and are used for flow control between the MSS COMM_BLK and PDMA channel. Data from the COMM_BLK receive FIFO going to any MSS memory-mapped locations, and the data from any MSS memory-mapped locations going to the COMM_BLK transmit FIFO can be transferred without using the Cortex-M3 processor or the system controller. The PDMA supports DMA transfers from embedded Nonvolatile Memory (eNVM) to the COMM_BLK to facilitate the initialization of fabric SRAMs—Micro SRAM (uSRAM) and Large SRAM (LSRAM).