9.2.3.3.2 Suspend/Resume by an LPM Transaction (L0 to L1 State Transition)

Suspend/Resume When Operating as a Peripheral

Entry into Suspend mode: When operating as a peripheral, the USB controller never initiates an LPM suspend (transition from the L0 state to the L1 state). Rather, the USB controller only suspends at the request of the host. However, for this to occur, the LPM feature must be enabled by setting up Table 9-117 appropriately. The LPMEN field in LPM_CTRL_REG is used to enable the extended and LPM transactions. The LPMXMT field in LPM_CTRL_REG is used to instruct the hardware that it is ready to suspend and to respond to the next LPM transaction with an ACK. In this case, the USB controller responds to the next LPM transaction with an ACK, if all other conditions are met. The response to an LPM transaction by the USB controller is summarized in the following table.
Table 9-4. Response to LPM Transaction as Peripheral
LPMXMT LPMEN Data Pending (Data Resides in Transmit FIFOs) Response to the Next LPM transaction
1'b0 00 Don't Care Timeout
1'b0 10
1'b1 00
1'b1 10
1'b0 01 Don't Care STALL
1'b1
1'b0 11 Don't Care NYET
1'b1 Yes NYET
1'b1 No ACK

For all cases shown in the preceding table in which the USB controller responds (no timeout occurs), an LPM interrupt is generated in LPM_INTR_REG (Table 9-119).

Important: The USB controller responds with an ACK only if there is no data pending in any of the transmit endpoint FIFOs. If there is data pending, the USB controller responds with a NYET.

Once an LPM transaction is successfully received, three events occur:

  1. Table 9-116 is updated with values received in the LPM transaction. The fields in this register are as follows:
    • LinkState: This field tells the USB controller what state to transition to. The only valid value for this field is 4’h1, indicating that the core must suspend. For any other value, the USB controller responds with a STALL, and the appropriate interrupt will be generated. However, in this case the LPM_ATTR_REG is updated so that software can observe the non-compliant LPM packet payload. In addition, the LPMERR interrupt set in Table 9-120 is also generated, informing software of the non-compliant LPM transaction.
    • HIRD: This field let the USB controller know the minimum duration that the host drives resume signaling on the bus. This field represents a resume duration range from 50 µs to 1200 µs. This value may be different for subsequent LPM transactions.
    • RmtWak: This is a 1-bit field indicating if the remote wake-up by the USB controller is allowed. This bit applies to the current suspend/resume cycle only. This bit may be different for subsequent LPM transactions. This bit must not supersede the wake-up capability that was previously negotiated on enumeration of the USB controller.
  2. The USB controller suspends 9 µs after transmitting the ACK. Resume signaling can be driven by the host or the USB controller 50 µs after this event. During this 9 µs interval, the host may continue to transmit the LPM transaction. The USB controller responds with an ACK in this case, regardless of the LPMXMT value in Table 9-117.
  3. An interrupt is generated, informing software of the response (an ACK in this case). An ACK response is the indication to the software that the USB controller has suspended.

Since the primary purpose of LPM is to save power, the software will read the Table 9-116 to determine the attributes of the suspend mode. The software must make a determination based on these attributes whether additional power savings in the system can be exploited.

Important: If the host initiates resume signaling, the USB controller is required to respond to the packet transmissions within the time specified by HIRD + 10 µs.
  • Resume Signaling Occurs on the Bus: When the host resumes the bus, it drives resume signaling for a minimum time specified by the HIRD field in Table 9-116. The USB controller must be able to respond to traffic within the time HIRD + 10 µs. The USB controller transitions to a normal operating state automatically and a resume interrupt is generated in Table 9-120. However, for this to occur, the inputs CLK and XCLK must be available. To facilitate the resume timing requirement, an additional feature, LPMNAK, is provided in Table 9-117. If LPMNAK is set to 1, all endpoints respond to any transaction (other than an LPM) with a NAK. This bit only takes effect after the USB controller has LPM suspended. Typically, this bit is asserted when the LPMXMT field is also asserted. Using this feature may simplify the resume timing requirement because only XCLK is needed for the USB controller to respond (with a NAK) to traffic. The software can continue to restore the system to normal operation while the USB controller responds to all transactions with a NAK. After the system is completely restored, the software can then clear the LPMNAK field in LPM_CTRL_REG.
  • Initiating Remote Wake-Up: If the software wants to initiate a remote wake-up while the USB controller is in Suspend mode, it must write a 1 to the LPMRES bit in Table 9-117. This bit is self clearing. Writing a 1 causes resume signaling to be driven on the bus for 50 µs. The host responds by driving resume signaling for 60 µs to 990 µs. 10 µs after the host stops driving resume, the USB controller transits to its normal operational state and is ready for packet transmission. A resume interrupt is generated in Table 9-120.

Suspend/Resume When Operating as a Host

  • Entry into Suspend mode: When operating as a host, the controller initiates an LPM suspend (transition from the L0 state to the L1 state) by initiating the following LPM transaction:
    1. Software sets-up the desired attributes of the Suspend mode in Table 9-116. Enables remote wake-up and a large HIRD gives the peripheral more opportunity to conserve power.
    2. All LPM interrupts must be enabled in Table 9-119.
    3. Software must initiate the transaction by writing a 0x01 to Table 9-118.
    4. An interrupt is generated to inform software of the response to the LPM transaction. If an ACK is received, the controller will be suspended automatically within 8 µs. This is the indication that the controller is suspended.
    5. If the response from the device has a bit stuff error or a PID error, an LPMERR interrupt (Table 9-121) is generated. The hardware immediately attempts the LPM transaction for two more times. The device is not suspended for 8 µs after the initial LPM, so it will be able to respond to either of these subsequent LPM transactions. If an LPM timeout occurs three times, the LPMNC and the LPMERR interrupts are set (LPM_INTR_REG). At this time, software is unaware of the device state and must deduce it by other means.
  • Sending Resume Signaling: Resume signaling must be generated by the software as follows:
    1. All LPM interrupts must be enabled in Table 9-119.
    2. Software must write the LPMRES bit in Table 9-118. This bit is self clearing. This causes resume signaling to be generated on the bus for the time that is currently specified in the HIRD field in Table 9-116. Hardware assumes that this value was used in the last LPM transaction that caused the Suspend mode.
    3. After HIRD + 10 µs, the controller transitions to its normal operational state and is ready for packet transmission. A resume interrupt is generated in LPM_INTR_REG.
    Important: Prior to resuming, the software must ensure that the system is completely restored from a low- power state and that the inputs CLK and XCLK are available.
  • Responding to Remote Wake-Up: If the remote wake-up feature is enabled in the LPM transaction that caused the Suspend mode, the device may drive resume signaling on the bus. When this occurs, the device drives the resume signaling bus for 50 µs. The controller immediately begins driving resume signaling on the bus and will do so for 60 µs. 10 µs after completion of the resume signaling, the controller transitions to its normal operating state and is ready for packet transmission. At this time, the resume interrupt is generated in LPM_INTR_REG.