9.3.14.4 LPM_CTRL_REG (Host) Bit Definitions
| Bit Number | Name | Reset Value | Function |
|---|---|---|---|
| [7:2] | Reserved | N/A | |
| 1 | LPMRES | 0 | Initiates a RESUME from the L1 state. This bit differs from the classic RESUME bit (POWER_REG.bit2) in that the RESUME signal timing is controlled by hardware. When software writes this bit, resume signaling is asserted for a time specified by the HIRD field (LPM_ATTR_REG.bit[7:4]). This bit is self clearing. |
| 0 | LPMXMT | 0 | Transmits an LPM transaction. This bit is self clearing. This bit will be immediately cleared upon receipt of any token or three timeouts have occurred. |