9.3.14.3 LPM_CTRL_REG (Peripheral) Bit Definitions

Table 9-117. LPM_CTRL_REG (0x40043362)(Peripheral)
Bit Number	Name	Reset Value	Function
[7:5]	Reserved	NA	—
4	LPMNAK	0	Places all endpoints in a state such that the response to all transactions other than an LPM transaction is a NAK. This bit takes effect only after the USB controller has been LPM suspended. In this case, the USB controller continues to NAK until this bit has been cleared by software.
[3:2]	LPMEN	0	Enables LPM in the USB controller. There are three levels in which LPM can be enabled, which determines the response of the USB controller to LPM transactions. Following are the three levels: 00: LPM and extended transactions are not supported. In this case, the USB controller does not respond to LPM transactions and the transaction timeouts. 01: LPM and extended transactions are not supported. In this case, the USB controller does not respond to LPM transactions and the transaction timeouts. 10: LPM is not supported but extended transactions are supported. In this case, the USB controller responds to an LPM transaction with a STALL. 11: The USB controller supports LPM extended transactions. In this case, the USB controller responds with a NYET or an ACK as determined by the value of LPMXMT (bit 0 of this register) and other conditions.
1	LPMRES	0	Initiates resume (remote wake-up). This bit differs from the classic RESUME bit (POWER_REG.bit2) in that the RESUME signal timing is controlled by hardware. When software writes this bit, resume signaling is asserted for 50 µs. This bit is self clearing.
0	LPMXMT	0	Instructs the USB controller to transition to the L1 state upon the receipt of the next LPM transaction. This bit is only effective if LPMEN (bits[3:2] of this register) is set to 11. This bit can be set in the same cycle as LPMEN. If this bit is set to 1 and LPMEN = 11, the USB controller can respond in the following ways: If any data is not pending (all transmit FIFOs are empty), the USB controller will respond with an ACK. In this case this bit will self clear and a software interrupt will be generated. If any data is pending (data resides in at least one transmit FIFO), the USB controller will respond with a NYET. In this case, this bit will NOT self clear; however, a software interrupt will be generated.

[7:5]

Reserved

NA

—

4

LPMNAK

0

Places all endpoints in a state such that the response to all transactions other than an LPM transaction is a NAK. This bit takes effect only after the USB controller has been LPM suspended. In this case, the USB controller continues to NAK until this bit has been cleared by software.

[3:2]

LPMEN

0

Enables LPM in the USB controller. There are three levels in which LPM can be enabled, which determines the response of the USB controller to LPM transactions. Following are the three levels:

00: LPM and extended transactions are not supported. In this case, the USB controller does not respond to LPM transactions and the transaction timeouts.

01: LPM and extended transactions are not supported. In this case, the USB controller does not respond to LPM transactions and the transaction timeouts.

10: LPM is not supported but extended transactions are supported. In this case, the USB controller responds to an LPM transaction with a STALL.

11: The USB controller supports LPM extended transactions. In this case, the USB controller responds with a NYET or an ACK as determined by the value of LPMXMT (bit 0 of this register) and other conditions.

1

LPMRES

0

Initiates resume (remote wake-up). This bit differs from the classic RESUME bit (POWER_REG.bit2) in that the RESUME signal timing is controlled by hardware. When software writes this bit, resume signaling is asserted for 50 µs. This bit is self clearing.

0

LPMXMT

0

Instructs the USB controller to transition to the L1 state upon the receipt of the next LPM transaction. This bit is only effective if LPMEN (bits[3:2] of this register) is set to 11. This bit can be set in the same cycle as LPMEN. If this bit is set to 1 and LPMEN = 11, the USB controller can respond in the following ways:

If any data is not pending (all transmit FIFOs are empty), the USB controller will respond with an ACK. In this case this bit will self clear and a software interrupt will be generated.

If any data is pending (data resides in at least one transmit FIFO), the USB controller will respond with a NYET. In this case, this bit will NOT self clear; however, a software interrupt will be generated.