11.6.7 Receive Message Control and Command Register
Each receive buffer is configured through a set of registers. Those registers are broken down into a Command/Control register, Identifier register, Data high register, and Data low register, Acceptance Mask Register (AMR), Acceptance Code Register (ACR), AMR data, ACR data. The following tables provide a detailed description of receive message0 buffer registers bits.
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:24] | Reserved | 0 | Reserved |
| 23 | WPNH | 1 | Write protect not high 0: Bit[21:16] remain unchanged 1: The write protect is not set and bit[21:16] are modified, default The read back value of this bit is undefined |
| 22 | Reserved | 0 | Reserved |
| 21 | RTR | 0 | RTR bit; Control bit 0: This is a regular message 1: This is an RTR message |
| 20 | IDE | 0 | Extended identifier bit; Control bit 0: This is a standard format message 1: This is an extended format message |
| [19:16] | DLC | 0 | Data length code; Control bits 0: Message has 0 data byte 1: Message has 1 data byte ... 8: Message has 8 data bytes 9-15: Message has 8 data bytes |
| [15:8] | Reserved | 0 | Reserved |
| 7 | WPNL | 1 | Write protect not low 0: Bits[6:3] remain unchanged 1: This write protect is not set and bits[6:3] are modified, default. This bit is always zero for read back |
| 6 | LF | 0 | Link flag; Control bit 0: This buffer is not linked to the next buffer 1: This buffer is linked with the next buffer |
| 5 | RxIntEbl | 0 | Receive interrupt enable; Control bit 0: Interrupt generation is disabled 1: Interrupt generation is enabled |
| 4 | RTRreply | 0 | Automatic message reply upon receipt of an RTR message; Control bit 0: Automatic RTR message handling disabled 1: Automatic RTR message handling enabled |
| 3 | TxBufferEbl | 0 | Transaction buffer enable; Control bit 0: Buffer is disabled 1: Buffer is enabled |
| 2 | RTRabort | 0 | RTR abort request; Command bit 0: Idle 1: Requests removal of a pending RTR message reply. The flag is cleared when the message was removed or when the message won arbitration. The TxReq flag is cleared at the same time |
| 1 | RTRP | 0 | RTReply pending; Command bit 0: No RTR reply request pending 1: RTR reply request pending |
| 0 | MsgAv/RTRS | 0 | Message available/RTR sent; Command bit If RTRreply flag is set, this bit shows if an RTR auto-reply message has been sent, otherwise it indicates if the buffer contains a valid message. Read 0: Idle 1: New message available (RTRreply = 0), RTR auto-reply message sent (RTRreply = 1) Write 0: Idle 1: Acknowledges receipt of new message or transmission of RTR auto-reply message. Before acknowledging receipt of a new message, the message content must be copied into system memory. Acknowledging a message clears the MsgAv flag. |
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:3] | ID[28:0] | RxMessage0 buffer identifier. For extended frame, the received message ID is stored in [31:3]. For standard frame, the message ID is stored in [31:21]. | |
| [2:0] | Reserved | 0 | N/A |
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:0] | RX_MSG0_DATA_HIGH | [31:24]: CAN data byte 1 [23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 | The byte mapping can be set using the CAN swap_endian configuration bit. swap_endian = 0, default: [31:24]: CAN data byte 1 [23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1 [31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2 [7:0]: CAN data byte 1 |
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:0] | RX_MSG0_DATA_LOW | [31:24]: CAN data byte 5 [23:16]: CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 | The byte mapping can be set using the CAN swap_endian configuration bit. swap_endian = 0, default: [31:24]: CAN data byte 5 [23:16]: CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1 [31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6 [7:0]: CAN data byte 5 |
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:0] | RX_MSG0_AMR | Receive Message0 buffer AMR bits [31:3]: Identifier [2]: IDE [1]: RTR [0]: Reserved AMR: 0: The incoming bit is checked against the respective ACR. The message is not accepted when the incoming bit does not match with the respective ACR flag. 1: The incoming bit is a “don't care” |
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:0] | RX_MSG0_ACR | Receive Message0 buffer ACR bits [31:3]: Identifier [2]: IDE [1]: RTR [0]: N/A |
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:0] | RX_MSG0_AMR_DATA | Receive Message0 buffer AMR Data bits [15:8]: CAN data byte 1 [7:0]: CAN data byte 2 |
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:0] | RX_MSG0_ACR_DATA | Receive Message0 buffer ACR Data bits [15:8]: CAN data byte 1 [7:0]: CAN data byte 2 |
The rest of the receive message buffers (RX_MSG1 to RX_MSG31) and register bits have the same descriptions as the RX_MSG0 registers shown above. The following table lists the address offset for the RX_MSG1 to RX_MSG31 registers.
| Register Name | Address Offset | R/W | Reset Value | Description |
|---|---|---|---|---|
| RX_MSG1 Buffer | 0x240-0x25C | R/W | 0 | Receive Message1 buffer registers |
| RX_MSG2 Buffer | 0x260-0x27C | R/W | 0 | Receive Message2 buffer registers |
| RX_MSG3 Buffer | 0x280-0x29C | R/W | 0 | Receive Message3 buffer registers |
| RX_MSG4 Buffer | 0x2A0-0x2BC | R/W | 0 | Receive Message4 buffer registers |
| RX_MSG5 Buffer | 0x2C0-0x2DC | R/W | 0 | Receive Message5 buffer registers |
| RX_MSG6 Buffer | 0x2E0-0x2FC | R/W | 0 | Receive Message6 buffer registers |
| RX_MSG7 Buffer | 0x300-0x31C | R/W | 0 | Receive Message7 buffer registers |
| RX_MSG8 Buffer | 0x320-0x33C | R/W | 0 | Receive Message8 buffer registers |
| RX_MSG9 Buffer | 0x340-0x35C | R/W | 0 | Receive Message9 buffer registers |
| RX_MSG10 Buffer | 0x360-0x37C | R/W | 0 | Receive Message10 buffer registers |
| RX_MSG11 Buffer | 0x380-0x39C | R/W | 0 | Receive Message11 buffer registers |
| RX_MSG12 Buffer | 0x3A0-0x3BC | R/W | 0 | Receive Message12 buffer registers |
| RX_MSG13 Buffer | 0x3C0-0x3DC | R/W | 0 | Receive Message13 buffer registers |
| RX_MSG14 Buffer | 0x3E0-0x3FC | R/W | 0 | Receive Message14 buffer registers |
| RX_MSG15 Buffer | 0x400-0x41C | R/W | 0 | Receive Message15 buffer registers |
| RX_MSG16 Buffer | 0x420-0x43C | R/W | 0 | Receive Message16 buffer registers |
| RX_MSG17 Buffer | 0x440-0x45C | R/W | 0 | Receive Message17 buffer registers |
| RX_MSG18 Buffer | 0x460-0x47C | R/W | 0 | Receive Message18 buffer registers |
| RX_MSG19 Buffer | 0x480-0x49C | R/W | 0 | Receive Message19 buffer registers |
| RX_MSG20 Buffer | 0x4A0-0x4BC | R/W | 0 | Receive Message20 buffer registers |
| RX_MSG21 Buffer | 0x4C0-0x4DC | R/W | 0 | Receive Message21 buffer registers |
| RX_MSG22 Buffer | 0x4E0-0x4FC | R/W | 0 | Receive Message22 buffer registers |
| RX_MSG23 Buffer | 0x500-0x51C | R/W | 0 | Receive Message23 buffer registers |
| RX_MSG24 Buffer | 0x520-0x53C | R/W | 0 | Receive Message24 buffer registers |
| RX_MSG25 Buffer | 0x540-0x55C | R/W | 0 | Receive Message25 buffer registers |
| RX_MSG26 Buffer | 0x560-0x57C | R/W | 0 | Receive Message26 buffer registers |
| RX_MSG27 Buffer | 0x580-0x59C | R/W | 0 | Receive Message27 buffer registers |
| RX_MSG28 Buffer | 0x5A0-0x5BC | R/W | 0 | Receive Message28 buffer registers |
| RX_MSG29 Buffer | 0x5C0-0x5DC | R/W | 0 | Receive Message29 buffer registers |
| RX_MSG30 Buffer | 0x5E0-0x5FC | R/W | 0 | Receive Message30 buffer registers |
| RX_MSG31 Buffer | 0x600-0x61C | R/W | 0 | Receive Message31 buffer registers |
See the RX_MSG0 buffer for description from Table 11-16 through Table 11-23.