11.6.2 CAN Controller Registers
This section describes the register and bit description of various categories of registers in the CAN controller. In addition, system registers which are applicable to CAN are described in this section. This provides programmers the view for firmware development. Microchip recommends using drivers provided in the tool set for application development.
The CAN base address resides at 0x40015000 and extends to address 0x40015FFF in the Cortex-M3 processor memory map. The registers set in the CAN controller are summarized in the following table.
| Register Name | Address | R/W | Reset Value | Description |
|---|---|---|---|---|
| Table 11-8 | 0x018 | R/W | 0 | CAN configuration register. The CAN controller has to be configured prior to its use. The configuration includes effective CAN data rate, CAN data synchronization, and message buffer arbitration. This register has to be configured before the CAN controller is started (Run mode). Run or STOP of the CAN controller is a different action than reset. See Command Register for more details. |
| Table 11-9 | 0x014 | R/W | 0 | The CAN controller is used in different operating modes. By disabling transmitting data, it is possible to use the CAN in Listen-only mode, enabling features such as automatic bit rate detection. Before starting the CAN controller, all the CAN configuration registers have to be set according to the target application. |
| Table 11-10 | 0x020 | R/W | 0 | Transmit Message0 buffer control and command register |
| Table 11-11 | 0x024 | R/W | 0 | Transmit Message0 buffer identifier register |
| Table 11-12 | 0x028 | R/W | 0 | Transmit Message0 buffer data high register |
| Table 11-13 | 0x02C | R/W | 0 | Transmit Message0 buffer data low register |
| Table 11-15 | 0x0C | R | 0 | Transmit (TX) message buffer status. This bundles transmit request (TxReq) pending flags from all 32 receive message buffers. |
| Table 11-16 | 0x220 | R/W | 0 | Receive Message0 buffer command and control register |
| Table 11-17 | 0x224 | R/W | 0 | Receive Message0 buffer Identifier register |
| Table 11-18 | 0x228 | R/W | 0 | Receive Message0 buffer data high register |
| Table 11-19 | 0x22C | R/W | 0 | Receive Message0 buffer data low register |
| Table 11-20 | 0x230 | R/W | 0 | Acceptance Mask Register (AMR) The AMR register defines whether the incoming bit is checked against the ACR register |
| Table 11-21 | 0x234 | R/W | 0 | Acceptance Code Register (ACR) |
| Table 11-22 | 0x238 | R/W | 0 | AMR- Data |
| Table 11-23 | 0x23C | R/W | 0 | ACR- Data |
| Table 11-25 | 0x08 | R | 0 | Receive (RX) message buffer status. This bundles message available (MsgAv) flags from all 32 receive message buffers. |
| Table 11-26 | 0x01C | RW | 0 | Error capture register Can be used to perform additional CAN bus diagnostics |
| Table 11-27 | 0x010 | R | 0 | CAN error status indicator register Provides visibility into CAN controller error state, receive error count, and transmit error count. Special flags to report error counter values equal to or in excess of 96 errors are available to indicate heavily disturbed bus situations. |
| Table 11-28 | 0x004 | R/W | 0 | Interrupt enable register Writing 1 to a particular bit enables the corresponding interrupt source as set in INT_STATUS. |
| Table 11-29 | 0x00 | R/W | 0x00 | Interrupt status register Writing 1 to a particular bit sets the corresponding interrupt source. The associated enable bit in INT_ENABLE must also be set for this interrupt to be generated. |
The following sections describe the functionality and the bit description of each of the registers in more details.