11.6.5 Transmit Message Control and Command Register

Each transmit buffer gets configured through a set of registers. Those registers are broken down into a Control/Command register, Identifier register, Data high register, and Data low register. In the Command/Control register, some bits set a control flag and others set a command flag. The following tables provide a detailed description of transmit message0 buffer registers bits.

Important: The rest of the transmit messages (message1 to message31) follow the same registers definition as message0.

Table 11-10. TX_MSG0_CTRL_CMD
Bit Number	Name	Reset Value	Description
[31:24]	Reserved	0	Reserved
23	WPN	1	Write protect not 0: Bit[21:16] remain unchanged 1: The write protect is not set and bit[21:16] are modified, by default. The read back value of this bit is undefined Using the WPN flag enables simple retransmission of the same message by only setting the TxReq and TxAbort flags without taking care of the special flags
22	Reserved	0	Reserved
21	RTR	0	RTR; control flag bit 0: Standard message 1: RTR message
20	IDE	0	Extended identifier bit; Control flag bit 0: This is a standard format message 1: This is an extended format message
[19:16]	DLC	0	Data length code; Control flag bit Invalid values are transmitted as they are, but the number of data bytes is limited to eight 0: Message has 0 data bytes 1: Message has 1 data byte ... 8: Message has 8 data bytes 9-15: Message has 8 data bytes
[15:4]	Reserved	0	Reserved
3	WPN	1	Write protect not 0: Bit[2] remains unchanged 1: The write protect is not set and Bit[2] is modified, default.
2	TxIntEbl	0	Tx interrupt enable; Control flag bit 0: Interrupt is disabled 1: Interrupt is enabled, successful message transmission sets the TX_MSG flag in the interrupt controller
1	TxAbort	0	Transmit abort request; Command flag bit 0: Idle 1: Requests removal of a pending message The message is removed the next time an arbitration loss happens. The flag is cleared when the message is removed or when the message wins arbitration. The TxReq flag is cleared at the same time.
0	TxReq	0	Transmit request; Command flag bit Write: 0: Idle. No message transmit request. 1: Message transmit request The Tx message buffer must not be changed while TxReq is 1. Read: 0: TxReq completed 1: TxReq pending

Table 11-11. TX_MSG0_ID
Bit Number	Name	Reset Value	Description
[31:3]	ID[28:0]	0	Transmit message0 buffer identifier (29-bit wide)
[2:0]	Reserved	0	Reserved

Table 11-12. TX_MSG0_DATA_HIGH
Bit Number	Name	Reset Value	Description
[31:0]	TX_MSG0_DATA_HIGH	[31:24]: CAN data byte 1 [23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4	The byte mapping can be set using the CAN swap_endian configuration bit. swap_endian = 0, default [31:24]: CAN data byte 1 [23:16]: CAN data byte 2 [15:8]: CAN data byte 3 [7:0]: CAN data byte 4 swap_endian = 1 [31:24]: CAN data byte 4 [23:16]: CAN data byte 3 [15:8]: CAN data byte 2 [7:0]: CAN data byte 1

Table 11-13. TX_MSG0_DATA_LOW
Bit Number	Name	Reset Value	Description
[31:0]	TX_MSG0_DATA_LOW	[31:24]: CAN data byte 5 [23:16]: CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8	The byte mapping can be set using the CAN swap_endian configuration bit swap_endian = 0, default [31:24]: CAN data byte 5 [23:16]: CAN data byte 6 [15:8]: CAN data byte 7 [7:0]: CAN data byte 8 swap_endian = 1 [31:24]: CAN data byte 8 [23:16]: CAN data byte 7 [15:8]: CAN data byte 6 [7:0]: CAN data byte 5

The rest of the transmit message buffers (TX_MSG1 to TX_MSG31) registers and registers bits have the same descriptions as the TX_MSG0 registers shown above.

The following table lists the address offsets for the TX_MSG1 to TX_MSG31 registers.

Table 11-14. Transmit Message1 to Transmit Message31 Registers Description
Register Name	Address Offset	R/W	Description
TX_MSG1 Buffer	0x030-0x03C	R/W	Transmit Message1 buffer registers
TX_MSG2 Buffer	0x0040-0x04C	R/W	Transmit Message2 buffer registers
TX_MSG3 Buffer	0x050-0x05C	R/W	Transmit Message3 buffer registers
TX_MSG4 Buffer	0x060-0x06C	R/W	Transmit Message4 buffer registers
TX_MSG5 Buffer	0x070-0x07C	R/W	Transmit Message5 buffer registers
TX_MSG6 Buffer	0x080-0x08C	R/W	Transmit Message6 buffer registers
TX_MSG7 Buffer	0x090-0x09C	R/W	Transmit Message7 buffer registers
TX_MSG8 Buffer	0x0A0-0x0AC	R/W	Transmit Message8 buffer registers
TX_MSG9 Buffer	0x0B0-0x0BC	R/W	Transmit Message9 buffer registers
TX_MSG10 Buffer	0x0C0-0x0CC	R/W	Transmit Message10 buffer registers
TX_MSG11 Buffer	0x0D0-0x0DC	R/W	Transmit Message11 buffer registers
TX_MSG12 Buffer	0x0E0-0x0EC	R/W	Transmit Message12 buffer registers
TX_MSG13 Buffer	0x0F0-0x0FC	R/W	Transmit Message13 buffer registers
TX_MSG14 Buffer	0x100-0X10C	R/W	Transmit Message14 buffer registers
TX_MSG15 Buffer	0x110-0X11C	R/W	Transmit Message15 buffer registers
TX_MSG16 Buffer	0x120-0X12C	R/W	Transmit Message16 buffer registers
TX_MSG17 Buffer	0x130-0X13C	R/W	Transmit Message17 buffer registers
TX_MSG18 Buffer	0x140-0X14C	R/W	Transmit Message18 buffer registers
TX_MSG19 Buffer	0x150-0X15C	R/W	Transmit Message19 buffer registers
TX_MSG20 Buffer	0x160-0X16C	R/W	Transmit Message20 buffer registers
TX_MSG21 Buffer	0x170-0X17C	R/W	Transmit Message21 buffer registers
TX_MSG22 Buffer	0x180-0X18C	R/W	Transmit Message22 buffer registers
TX_MSG23 Buffer	0x190-0X19C	R/W	Transmit Message23 buffer registers
TX_MSG24 Buffer	0x1A0-0X1AC	R/W	Transmit Message24 buffer registers
TX_MSG25 Buffer	0x1B0-0X1BC	R/W	Transmit Message25 buffer registers
TX_MSG26 Buffer	0x1C0-0X1CC	R/W	Transmit Message26 buffer registers
TX_MSG27 Buffer	0x1D0-0X1DC	R/W	Transmit Message27 buffer registers
TX_MSG28 Buffer	0x1E0-0X1EC	R/W	Transmit Message28 buffer registers
TX_MSG29 Buffer	0x1F0-0X1FC	R/W	Transmit Message29 buffer registers
TX_MSG30 Buffer	0x200-0X20C	R/W	Transmit Message30 buffer registers
TX_MSG31 Buffer	0x210-0X21C	R/W	Transmit Message31 buffer registers

See TX_MSG0 buffer for description from Table 11-10 through Table 11-13.