11.6.3 Configuration Register
The CAN configuration register CAN_CONFIG is a 32-bit register that is used to configure the functionality of the CAN controller. The CAN controller has to be configured prior to its use. The following table shows the CAN_CONFIG register and summarizes the bit description within the register.
| Bit Number | Name | Description |
|---|---|---|
| 31 | Reserved | Reserved |
| [30:16] | CFG_BITRATE | Configuration bit rate Prescaler for generating the time quantum which defines the TQ: 0: One time quantum equals 1 clock cycle 1: One time quantum equals 2 clock cycles 32767: One time quantum equals 32768 clock cycles |
| 15 | Reserved | Reserved |
| 14 | ECR_MODE | Error-capture mode 0: Free running. The ECR register shows the current bit position within the CAN frame. 1: Capture mode. The ECR register shows the bit position and type of the last captured CAN error. |
| 13 | SWAP_ENDIAN | The byte position of the CAN receive and
transmit data fields can be modified to match the endian setting of the
processor or the used CAN protocol. 0: CAN data byte position is not swapped (big endian) 1: CAN data byte position is swapped (little endian) |
| 12 | CFG_ARBITER | Transmit buffer arbiter 0: Round robin arbitration 1: Fixed priority arbitration |
| [11:8] | CFG_TSEG1 | Time segment 1. Time segment 1 includes the
propagation time Length of the first time segment: tseg1 = CFG_TSEG1+1 CFG_TSEG1 = 0 and CFG_TSEG1 = 1 are not allowed |
| [7:5] | CFG_TSEG2 | Time segment 2 Length of the second time segment: tseg2 = CFG_TSEG2+1 CFG_TSEG2 = 0 is not allowed CFG_TSEG2 = 1 is only allowed in Direct-sampling mode |
| 4 | AUTO_RESTART | The CAN can be set to restart either “by
hand” or automatically after a bus-off. 0: After bus-off, the CAN must be restarted “by hand”. This is the recommended setting. 1: After bus-off, the CAN restarts automatically after 128 groups of 11 recessive bits. |
| [3:2] | CFG_SJW | Synchronization Jump Width 1 sjw ≤ tseg1 and sjw ≤ tseg2 |
| 1 | SAMPLING_MODE | CAN bus bit sampling 0: One sampling point is used in the receiver path 1: Three sampling points with majority decision are used |
| 0 | EDGE_MODE | CAN bus synchronization logic 0: Edge from ‘R’ to ‘D’ is used for synchronization 1: Both edges are used |