18.2.2.3 Interrupts

There are two interrupt signals from the system timer block—TIMER1INT and TIMER2INT. The TIMER1INT signal is mapped to INTISR[14] and the TIMER2INT signal is mapped to INTISR[15] in the Cortex-M3 processor Nested Vectored Interrupt Controller (NVIC) controller. Both interrupt enable bits within the NVIC (INTISR[14] and INTISR[15]) correspond to bit locations 14 and 15. These interrupts are enabled by setting the appropriate TIMxINTEN bits in TIM1_CTRL, TIM2_CTRL, or TIM64_CTRL registers.

In 32-bit mode, the TIMxRIS bit in the respective interrupt service routine must be cleared to prevent a reassertion of the interrupt. Similarly, in 64-bit mode, TIM64RIS bit in the respective interrupt service routine must be cleared to prevent a reassertion of the interrupt.