8.2.4.1 Peripheral to Memory Transfers/Memory to Memory Transfers

For peripheral to memory or peripheral to memory transfer, the DMA transfer starts if BUFFER_A_TRANSFER_COUNT or BUFFER_B_TRANSFER_COUNT is non-zero.

Before the transfer, the source address (CHANNEL_x_BUFFER_A_SRC_ADDR) and destination address (CHANNEL_x_BUFFER_B_DST_ADDR) of a channel are configured; then write to one of the transfer count registers to begin the DMA transaction. Alternatively, firmware can also write to the control register first and turn pause on, if needed, then turn it off later.

If the PAUSE bit in the Table 8-7 register is set, when you write a non-zero value to BUFFER_A_TRANSFER_COUNT or BUFFER_B_TRANSFER_COUNT, then the DMA transaction waits until PAUSE is cleared.

If bidirectional DMA of peripheral to memory (receive) and memory to peripheral (transmit) is desired, two channels must be programmed appropriately. In particular, the TRANSFER_SIZE fields in both the Table 8-7 registers must be programmed identically.

Channels can be assigned to peripherals or memory arbitrarily. For example, to receive only DMA data from one of the SPI ports, only one channel is required. In this case, the DIR bit in the CHANNEL_x_CONTROL register must be set to 0 (peripheral to memory) and the PERIPHERAL_SEL field must be set to 4 (SPI_0 receive to memory).