8.4.1.3 CHANNEL_x_CONTROL Register Bit Definition
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| [31:27] | Reserved | 0 | Software must not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit must be preserved across a read-modify-write operation. |
| [26:23] | PERIPHERAL_SEL | 0 | Selects the peripheral assigned to this channel. See Table 8-8. |
| 22 | Reserved | 0 | Reserved |
| [21:14] | WRITE_ADJ | 0 | This field contains a binary value, indicating the number of M3_CLK periods which the PDMA must wait after completion of a read or write access to a peripheral before evaluating the out-of-band status signals from that peripheral for another transfer. This is typically used to ensure that a posted write has fully completed to the peripheral in cases where the peripheral is running at a lower clock frequency than the PDMA. However, it may also be used to allow the PDMA to take account of internal latencies in the peripheral, where the ready status of a FIFO may not be available for a number of clock ticks after a read or write, due to internal synchronization delays, for example, within the peripheral. This applies particularly in the case of user-designed peripherals in the FPGA fabric. |
| [13:12] | DEST_ADDR_INC | 00 | This field controls the address increment at
the destination end of the DMA transfer. The values indicate: 00: 0 bytes 01: 1 byte 10: 2 bytes 11: 4 bytes |
| [11:10] | SRC_ADDR_INC | 00 | This field controls the address increment at
the source end of the DMA transfer. The values indicate: 00: 0 bytes 01: 1 byte 10: 2 bytes 11: 4 bytes |
| 9 | HI_PRIORITY | 0 | When asserted, this channel is treated as high priority by the arbitration state machine. |
| 8 | CLR_COMP_B | 0 | When asserted, clears the CH_COMP_B bit in the channel status register and the buffer status register for this buffer in this channel. This causes PDMAINTERRUPT to negate if not being held asserted by another channel. This bit always reads back as zero. |
| 7 | CLR_COMP_A | 0 | When asserted, clears the CH_COMP_A bit in the channel status register and the buffer status register for this buffer in this channel. This causes PDMAINTERRUPT to negate if not being held asserted by another channel. This bit always reads back as zero. |
| 6 | INTEN | 0 | When asserted, a DMA completion on this channel causes PDMAINTERRUPT to assert. |
| 5 | RESET | 0 | When asserted, resets this channel. Always reads back as zero. |
| 4 | PAUSE | 0 | When asserted, pauses the transfers for this channel. |
| [3:2] | TRANSFER_SIZE | 00 | This field determines the data width of each DMA transfer cycle for this DMA channel. The allowed values are: 00: Byte (8 bits) 01: Halfword (16 bits) 10: Word (32 bits) 11: Reserved |
| 1 | DIR | 0 | If PERIPHERAL_DMA = 1, then this bit is
valid. If so, then the values of this bit indicate: 0: Peripheral to memory 1: Memory to peripheral |
| 0 | PERIPHERAL_DMA | 0 | 0: Channel is configured for memory to memory DMA. 1: Channel is configured for peripheral DMA. Based on the value of DIR, the peripheral ready signal associated with this DMA channel is interpreted as initiating transfers either from memory to the peripheral or vice-versa. |
The following table gives the PERIPHERAL_SEL bits description.
| Bit 26 | Bit 25 | Bit 24 | Bit 23 | Function |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | From UART_0 receive to any MSS memory-mapped location. |
| 0 | 0 | 0 | 1 | From any MSS memory-mapped location to UART_0 transmit. |
| 0 | 0 | 1 | 0 | From UART_1 receive to any MSS memory-mapped location. |
| 0 | 0 | 1 | 1 | From any MSS memory-mapped location to UART_1 transmit. |
| 0 | 1 | 0 | 0 | From SPI_0 receive to any MSS memory-mapped location. |
| 0 | 1 | 0 | 1 | From any MSS memory-mapped location to SPI_0 transmit. |
| 0 | 1 | 1 | 0 | From SPI_1 receive to any MSS memory-mapped location. |
| 0 | 1 | 1 | 1 | From any MSS memory-mapped location to SPI_1 transmit. |
| 1 | 0 | 0 | 0 | To/from FPGA fabric peripheral on FIC_0 interface (DMAREADY_0[1]). |
| 1 | 0 | 0 | 1 | To/from FPGA fabric peripheral on FIC_0 interface (DMAREADY_0[0]). |
| 1 | 0 | 1 | 0 | From any MSS memory-mapped location to CAN. |
| 1 | 0 | 1 | 1 | From CAN to any MSS memory-mapped location. |
| 1 | 1 | 0 | 0 | To/from FPGA fabric peripheral on FIC_1 interface (DMAREADY_1[1]). |
| 1 | 1 | 0 | 1 | To/from FPGA fabric peripheral on FIC_1 interface (DMAREADY_1[0]). |
| 1 | 1 | 1 | 0 | From COMM_BLK receive to any MSS memory-mapped location. |
| 1 | 1 | 1 | 1 | From any MSS memory-mapped location to COMM_BLK transmit. |