8.2.4.2 Posted APB Writes
The AHB to APB bridges in the SmartFusion 2 device implement posted writes (also known as dump and run) for write accesses to peripherals. PDMA performs a write operation to a peripheral but the data is not written to the peripheral immediately. Therefore, the PDMA block must not start another DMA on this channel based on the state of the ready signal from that peripheral until the write is complete. The time window involved is variable, depending on the ratio of M3_CLK to PCLK, for each of the two peripheral buses. WRITE_ADJ in the 8.4.1.3 CHANNEL_x_CONTROL Register Bit Definition (Table 8-7) register is an 8-bit binary coded field used to define, for each DMA channel, how long to wait (in M3_CLKs) after each DMA transfer cycle before interpreting the ready signal for that DMA channel as representing a new request.
A suitable value for WRITE_ADJ depends on the target of the DMA transfer.
The following steps describe how to select the values:
The WRITE_ADJ value of 10 can be provided as a default value
- When the PDMA channel is configured for transfers with MSS peripherals.
- For DMA transfers with FPGA fabric implemented peripherals, making use
of the DMAREADY0 or DMAREADY1 fabric interface signals indicate that the peripheral is
ready for another DMA transfer.
The WRITE_ADJ parameter can be set to zero to achieve the maximum transfer speed for memory-to-memory transfers.
The internal latency of FPGA implemented peripherals decide the WRITE_ADJ value for fabric peripherals that do not use the DMAREADY0 or DMAREADY1 fabric interface signals.