20.3.1.3 SERDES L2/P2, PRST#

L2 and P2 are low power states for the Link and PHY interface in a PCI Express (PCIe) system. A power management component in a PCIe system will control exit from the L2/P2 state. Part of the sequence when emerging from the low power state involves assertion and release of the PCI Express Reset (PERST# or SDIFx_PERST_N in our implementation). CoreResetP monitors SDIFx_PERST signals and L2/P2 state and generates CORE reset and PHY reset to fulfill the low power mode reset requirement. The following figure shows the CoreResetP connectivity with SERDES_IF block. If the System Builder is used to generate the Libero project, all required cores are Instantiated, and connections are made automatically.