20.3.1.1 MSS_READY Generation

Any design which consists of MSS and a fabric subsystem must be synchronized to establish the communication between them. When MSS is doing any transaction, the fabric should be ready. Similarly, when fabric is doing any transaction, the MSS should be ready. The following figure shows the typical FIC subsystem with CoreResetP connectivity. CoreResetP generates the MSS_READY signal, which indicates that MSS is ready for communication. The MSS_READY signal is generated whenever a cold reset (power-up event or assertion of DEVRST_N) occurs or due to MSS reset (for example, a watchdog timeout event, the assertion of MSS_RESET_N_F2M, and so on). CoreResetP is relying on MSS_RESET_N_M2F and FIC_2_APB_M_PRESET_N signals to generate the MSS_READY signal.

If the user logic consists of any of the two DDR controllers (FDDR or MDDR) or Serial High speed controller (SERDESIF), the INIT_DONE signal should be used to reset the fabric subsystem. If none of MDDR/FDDR/SERDES is used, the MSS_READY signal should be used to reset the fabric subsystem. If the System Builder is used to generate the Libero project, all required cores are instantiated, and connections are made automatically.