2.5.3.2 Exception Types

The exception types are:

  • Reset: Reset is invoked on power-up or a warm reset. The exception model treats reset as a special form of exception. When reset is asserted, the operation of the processor stops, potentially at any point in an instruction. When reset is deasserted, execution restarts from the address provided by the reset entry in the vector table. Execution restarts as privileged execution in Thread mode.
  • NMI: A Non-Maskable Interrupt (NMI) can be signaled by a peripheral or triggered by software. This is the highest priority exception other than reset. It is permanently enabled and has a fixed priority of -2. NMIs cannot be:
    • Masked or prevented from activation by any other exception
    • Preempted by any exception other than Reset
  • HardFault: A HardFault is an exception that occurs because of an error during exception processing, or because an exception cannot be managed by any other exception mechanism. HardFaults have a fixed priority of -1, meaning they have higher priority than any exception with configurable priority.
  • MemManage: A MemManage fault is an exception that occurs because of a memory protection related fault. The MPU or the fixed memory protection constraints determines this fault, for both instruction and data memory transactions. This fault is always used to abort instruction accesses to Execute Never (XN) memory regions.
  • BusFault: A BusFault is an exception that occurs because of a memory related fault for an instruction or data memory transaction. This might be from an error detected on a bus in the memory system.
  • UsageFault: A UsageFault is an exception that occurs because of a fault related to instruction execution.
    This includes:
    • An undefined instruction
    • An illegal unaligned access
    • Invalid state on instruction execution
    • An error on exception return
    The following can cause a UsageFault when the core is configured to report them:
    • An unaligned address on word and halfword memory access
    • Division by zero
  • SVCall: A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an OS environment, applications can use SVC instructions to access OS kernel functions and device drivers.
  • PendSV: PendSV is an interrupt-driven request for system-level service. In an OS environment, use PendSV for context switching when no other exception is active.
  • SysTick: A SysTick exception is an exception the system timer generates when it reaches zero. Software can also generate a SysTick exception. In an OS environment, the processor can use this exception as system tick.
  • Interrupt (IRQ): A interrupt, or IRQ, is an exception signaled by a peripheral, or generated by a software request. All interrupts are asynchronous to instruction execution. In the system, peripherals use interrupts to communicate with the processor.

For an asynchronous exception, other than reset, the processor can execute another instruction between when the exception is triggered and when the processor enters the exception handler.

Table 2-16. Properties of the Different Exception Types
Exception number1 IRQ number1 Exception type Priority Vector address or offset2 Activation
1 — Reset -3, the highest 0x00000004 Asynchronous
2 -14 NMI -2 0x00000008 Asynchronous
3 -13 HardFault -1 0x0000000C
4 -12 MemManage Configurable 0x00000010 Synchronous
5 -11 BusFault Configurable3 0x00000014 Synchronous when precise, asynchronous when imprecise
6 -10 UsageFault Configurable3 0x00000018 Synchronous
7-10 Reserved — — —
11 -5 SVCall Configurable3 0x0000002C Synchronous
12-13 Reserved — — —
14 -2 PendSV Configurable3 0x00000038 Asynchronous
15 -1 SysTick Configurable3 0x0000003C Asynchronous
16 and above 0 and above Interrupt (IRQ) Configurable4 0x00000040 and above5 Asynchronous
Note:
  1. To simplify the software layer, the CMSIS only uses IRQ numbers and therefore uses negative values for exceptions other than interrupts. The IPSR returns the Exception number, see 2.5.1.3.7 Interrupt Program Status Register.
  2. See 2.5.3.4 Vector Table for more information.
  3. See 2.7.2.8 System Handler Priority Registers.
  4. See 2.7.1.8 Interrupt Priority Registers.
  5. Increasing in steps of 4.

Privileged software can disable the exceptions that Table 2-16 shows as having configurable priority. See 2.7.2.9 System Handler Control and State Register and 2.7.1.4 Interrupt Clear-enable Registers.

For more information about HardFaults, MemManage faults, BusFaults, and UsageFaults, see 2.5.4 Fault Handling.