2.7.2.8 System Handler Priority Registers
The SHPR1-SHPR3 registers set the priority level, 0 to 255 of the exception handlers that have configurable priority.
SHPR1-SHPR3 are byte accessible. See the register summary in Table 2-44 for their attributes.
The system fault handlers and the priority field and register for each handler are:
| Handler | Field | See |
|---|---|---|
| MemManage | PRI_4 | 2.7.2.8.2 System Handler Priority Register 2 |
| BusFault | PRI_5 | |
| UsageFault | PRI_6 | |
| SVCall | PRI_11 | 2.7.2.8.2 System Handler Priority Register 2 |
| PendSV | PRI_14 | 2.7.2.8.2 System Handler Priority Register 2 |
| SysTick | PRI_15 |
Each PRI_N field is 8 bits wide, but the processor implements only bits [7:M] of each field, and bits [M-1:0] read as zero and ignore writes.