2.7.2.8 System Handler Priority Registers

The SHPR1-SHPR3 registers set the priority level, 0 to 255 of the exception handlers that have configurable priority.

SHPR1-SHPR3 are byte accessible. See the register summary in Table 2-44 for their attributes.

The system fault handlers and the priority field and register for each handler are:

Table 2-53. System Fault Handler Priority Fields
HandlerFieldSee
MemManagePRI_4System Handler Priority Register 2
BusFaultPRI_5
UsageFaultPRI_6
SVCallPRI_11System Handler Priority Register 2
PendSVPRI_14System Handler Priority Register 2
SysTickPRI_15

Each PRI_N field is 8 bits wide, but the processor implements only bits [7:M] of each field, and bits [M-1:0] read as zero and ignore writes.