2.7.1.8 Interrupt Priority Registers

The NVIC_IPR0-NVIC_IPR59 registers provide an 8-bit priority field for each interrupt. These registers are byte-accessible. See the register summary in Table 2-34 for their attributes. Each register holds four priority fields as shown:

Figure 2-24. IPR Register Bit Assignments
Table 2-41. NVIC_IPR Bit Assignments
Bits Name Function
[31:24] Priority, byte offset 3 Each priority field holds a priority value, 0-255. The lower the value, the greater the priority of the corresponding interrupt. The processor implements only bits [7:n] of each field, bits [n-1:0] read as zero and ignore writes.
[23:16] Priority, byte offset 2
[15:8] Priority, byte offset 1
[7:0] Priority, byte offset 0

See 2.7.1.2 Accessing the Cortex-M3 Processor NVIC Registers Using CMSIS for more information about the access to the interrupt priority array, which provides the software view of the interrupt priorities.

Find the IPR number and byte offset for interrupt m as follows:

  • the corresponding IPRn number (see the preceding table), n is given by n = m DIV 4
  • the byte offset of the required Priority field in this register is m MOD 4, where:
    • byte offset 0 refers to register bits [7:0]
    • byte offset 1 refers to register bits [15:8]
    • byte offset 2 refers to register bits [23:16]
    • byte offset 3 refers to register bits [31:24].