2.7.1.4 Interrupt Clear-enable Registers

The NVIC_ICER0-NVIC_ICER7 registers disable interrupts, and show which interrupts are enabled. See the register summary in Table 2-34 for the register attributes.

The bit assignments are:

Figure 2-20. ICER Register Bit Assignments

Table 2-37. NVIC_ICER Bit Assignments
Bits	Name	Function
[31:0]	CLRENA	Interrupt clear-enable bits. Write: 0: no effect 1: disable interrupt. Read: 0: interrupt disabled 1: interrupt enabled.

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