7.2.2.3 Interrupt

There are two interrupts: HPD_XFR_CMP_INT and HPD_XFR_ERR_INT from the HPDMA to the NVIC on the Cortex-M3 processor. The interrupt signals are mapped to one of the IRQs in the Cortex-M3 NVIC controller.

The interrupt signals are also mapped to the dedicated interrupt signal MSS_INT_M2F[9] and the MSS_INT_M2F[22] of the fabric interface interrupt controller (FIIC).

This is to interrupt the user logic instantiated in the FPGA fabric. To enable HPDMA interrupts, the 9th bit (HPD_XFR_CMP_INT_EN) and the 22nd bit (HPD_XFR_CMP_INT_EN) of INTERRUPT_ENABLE0 register (located at address 0x40006000) has to be set. The status of the interrupts to FIIC can be determined by reading the 9th and 22nd bits of the INTERRUPT_REASON0 register (located at 0x40006008).

To determine the descriptor transfer status, monitor the Descriptor status register (HPDMADXSR, where X is 0 to 3). Before start of transaction, the enabled Descriptor interrupt bits are to be cleared. See Table 7-24 for clearing interrupts.