13.4.2 SPI Register Summary

The following table summarizes each of the SPI registers described in this document. The SPI_0 base address resides at 0x40001000 and extends to address 0x40001FFF in the Cortex-M3 processor memory map. The SPI_1 base address resides at 0x40011000 and extends to address 0x40011FFF in the Cortex-M3 processor memory map.

Table 13-8. SPI Register Summary
Register Name	Address Offset	R/W	Reset Value	Description
Table 13-9	0x00	R/W	0x80000102	Control register
Table 13-10	0x04	R/W	0x04	Transmit and receive data frame size
Table 13-11	0x08	R	0x2440	Status register
Table 13-12	0x0C	W	0x0	Interrupt clear register
Table 13-13	0x10	R	0x0	Receive data register
Table 13-14	0x14	W	0x0	Transmit data register
Table 13-15	0x18	R/W	0x07	Output clock generator (master mode)
Table 13-17	0x1C	R/W	0x0	Specifies slave selected (master mode)
Table 13-18	0x20	R	0x0	Masked interrupt status
Table 13-19	0x24	R	0x0	Raw interrupt status
Table 13-20	0x28	R/W	0x0	Control bits for enhanced modes
Table 13-21	0x2C	R/W	0x0	Command register
Table 13-22	0x30	R/W	0x0	Packet size
Table 13-23	0x34	R/W	0x0	Command size
Table 13-24	0x38	R/W	0x0	Slave hardware status
Table 13-25	0x3C	R	0x44	Status register
CTRL0	0x40	R/W	0x02	Aliased Table 13-9 register bits 7:0. This register allows byte operations from an 8-bit processor in the fabric. It is not intended for access from internal MSS masters.
CTRL1	0x44	R/W	0x01	Aliased Table 13-9 register bits 15:8. This register allows byte operations from an 8-bit processor in the fabric. It is not intended for access from internal MSS masters.
CTRL2	0x48	R/W	0x0	Aliased Table 13-9 register bits 23:16. This register allows byte operations from an 8-bit processor in the fabric. It is not intended for access from internal MSS masters.
CTRL3	0x4C	R/W	0x0	Aliased Table 13-9 register bits 25:24. This register allows byte operations from an 8-bit processor in the fabric. It is not intended for access from internal MSS masters.