1.7.1.5 Trace Port Interface Unit (TPIU) Configuration
TRACECLK & TRACEDATA[3:0] can be exposed to the FPGA fabric. TACECLK can be configured for these signals by using the Libero software, as shown in Figure 1-3.
Important: If the user design is using the FPGA fabric based
master, the Cortex-M3 processor requires a valid program in eNVM (from eNVM start address
0x60000000) to execute at power-up or power-on reset. The valid program can be a simple
user boot code or a simple loop program. You can select a
.hex file of a
valid program for eNVM data client using the SystemBuilder.