40.8.23 SDHC Auto CMD Error Status Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | ACESR |
| Offset: | 0x3C |
| Reset: | 0x0000 |
| Property: | - |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CMDNI | ACMDIDX | ACMDEND | ACMDCRC | ACMDTEO | ACMD12NE | ||||
| Access | R | R | R | R | R | R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – CMDNI Command Not Issued by Auto CMD12 Error
Setting this bit to 1 means CMD_wo_DAT is not executed due to an Auto CMD12 error (SDHC_ACESR[4:1]). This bit is set to 0 when Auto CMD Error is generated by Auto CMD23.
| Value | Description |
|---|---|
| 0 |
No error |
| 1 |
Error |
Bit 4 – ACMDIDX Auto CMD Index Error
This bit is set to 1 when the Command Index error occurs in response to a command.
| Value | Description |
|---|---|
| 0 |
No error |
| 1 |
Error |
Bit 3 – ACMDEND Auto CMD End Bit Error
This bit is set to 1 when detecting that the end bit of the command response is 0.
| Value | Description |
|---|---|
| 0 |
No error |
| 1 |
Error |
Bit 2 – ACMDCRC Auto CMD CRC Error
This bit is set to 1 when detecting a CRC error in the command response.
Bit 1 – ACMDTEO Auto CMD Timeout Error
This bit is set to 1 if no response is returned within 64 SDCLK cycles from the end bit of the command. If this bit is set to 1, the other error status bits (SDHC_ACESR[4:2]) are meaningless.
| ACMDCRC | ACMDTEO | Types of error |
|---|---|---|
| 0 | 0 | No error |
| 0 | 1 | Response Timeout error |
| 1 | 0 | Response CRC error |
| 1 | 1 | CMD line conflict |
Bit 0 – ACMD12NE Auto CMD12 Not Executed
If a memory multiple block data transfer is not started due to a command error, this bit is not set to 1 because it is not necessary to issue Auto CMD12. Setting this bit to 1 means the peripheral cannot issue Auto CMD12 to stop a memory multiple block data transfer due to some error. If this bit is set to 1, other error status bits (SDHC_ACESR[4:1]) are meaningless.
This bit is set to 0 when an Auto CMD error is generated by Auto CMD23.
| Value | Description |
|---|---|
| 0 |
No error |
| 1 |
Error |