40.8.7 SDHC_Response Register x

Table 40-8. Register Bit Attribute Legend
Symbol Description Symbol Description Symbol Description
R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented
W Writable bit HS Set by Hardware X Bit is unknown at Reset
K Write to clear S Software settable bit — —
Name: RRx
Offset: 0x10 + x*0x04 [x=0..3]
Reset: 0x000000000
Property: -

Bit 3130292827262524 
 CMDRESP[31:24] 
Access RRRRRRRR 
Reset 00000000 
Bit 2322212019181716 
 CMDRESP[23:16] 
Access RRRRRRRR 
Reset 00000000 
Bit 15141312111098 
 CMDRESP[15:8] 
Access RRRRRRRR 
Reset 00000000 
Bit 76543210 
 CMDRESP[7:0] 
Access RRRRRRRR 
Reset 00000000 

Bits 31:0 – CMDRESP[31:0] Command Response

The table below describes the mapping of command responses from the SD/SDIO/e.MMC bus to these registers for each responses type. In this table, R[] refers to a bit range of the response data as transmitted on the SD/SDIO/e.MMC bus.

Type of response Meaning of response Response field Response register
R1, R1b (normal response) Card Status R[39:8] SDHC_RR0[31:0]
R1b (Auto CMD12 response) Card Status for Auto CMD12 R[39:8] SDHC_RR3[31:0]
R1 (Auto CMD23 response) Card Status for Auto CMD23 R[39:8] SDHC_RR3[31:0]
R2 (CID, CSD register) CID or CSD register R[127:8] SDHC_RR0[31:0]

SDHC_RR1[31:0]

SDHC_RR2[31:0]

SDHC_RR3[23:0]
R3 (OCR register) OCR register for memory R[39:8] SDHC_RR0[31:0]
R4 (OCR register) OCR register for I/O R[39:8] SDHC_RR0[31:0]
R5, R5b SDIO response R[39:8] SDHC_RR0[31:0]
R6 (Published RCA response) New published RCA[31:16] and Card status bits R[39:8] SDHC_RR0[31:0]