40.8.24 SDHC Host Control 2 Register: SD/SDIO

Note: The content of the SDHC_HC2R register is depending on the mode. This description is for SD/SDIO mode.
Table 40-26. Register Bit Attribute Legend
Symbol Description Symbol Description Symbol Description
R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented
W Writable bit HS Set by Hardware X Bit is unknown at Reset
K Write to clear S Software settable bit — —
Name: HC2R
Offset: 0x3E
Reset: 0x0000
Property: -

Bit 15141312111098 
 PVALENASINTEN       
Access R/WR/W 
Reset 00 
Bit 76543210 
          
Access  
Reset  

Bit 15 – PVALEN Preset Value Enable

As the operating SDCLK frequency depend on the system implementation, it is difficult to determine these parameters in the standard host driver. When Preset Value Enable (PVALEN) is set to 1, automatic SDCLK frequency generation performed without considering system-specific conditions. This bit enables the functions defined in SDHC_PVR.

If this bit is written to 0, the Clock Generator Select bit (SDHC_CCR.CLKGSEL) and the SDCLK Frequency Select bit (SDHC_CCR.SDCLKFSEL) in the Clock Control Register (SDHC_CCR) are selected by the user.

If this bit is set to 1, SDHC_CCR.SDCLKFSEL and SDHC_CCR.CLKGSEL and SDHC_HC2R.DRVSEL are set by the peripheral as specified in the Preset Value Register (SDHC_PVR).

ValueDescription
0

SDHC_CCR.SDCLK, SDHC_CCR.SDCLKFSEL controlled by the user.
1

Automatic selection by Preset Value is enabled.

Bit 14 – ASINTEN Asynchronous Interrupt Enable

This bit can be set to 1 if a card support asynchronous interrupts and Asynchronous Interrupt Support (ASINTSUP) is set to 1 in SDHC_CA0R. Asynchronous interrupt is effective when DAT[1] interrupt is used in 4-bit SD mode. If this bit is set to 1, the user can stop the SDCLK during the asynchronous interrupt period to save power. During this period, the peripheral continues to deliver the Card Interrupt to the host when it is asserted by the card.

ValueDescription
0

Disabled
1

Enabled