40.8.35 SDHC Additional Present State Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | APSR |
| Offset: | 0x200 |
| Reset: | 0x0000000F |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| HDATLL[3:0] | |||||||||
| Access | R | R | R | R | |||||
| Reset | 1 | 1 | 1 | 1 | |||||
Bits 3:0 – HDATLL[3:0] High Line Level
This status is used to check the DAT[7:4] line level to recover from errors, and for debugging.