40.8.16 SDHC Software Reset Register

Only part of a data circuit is reset. The DMA circuit is also reset.

The following registers and bits are cleared by this bit:

• Buffer Data Port Register SDHC_BDPR: BUFDATA is cleared and initialized.
• Present State Register SDHC_PSR:
  • Buffer Read Enable (BUFRDEN)
  • Buffer Write Enable (BUFWREN)
  • Read Transfer Active (RTACT)
  • Write Transfer Active (WTACT)
  • DAT Line Active (DATLL)
  • Command Inhibit - DAT (CMDINHD)
• Block Gap Control Register SDHC_BGCR:
  • Continue Request (CONTR)
  • Stop At Block Gap Request (STPBGR)
• Normal Interrupt Status Register SDHC_NISTR:
  • Buffer Read Ready (BRDRDY)
  • Buffer Write Ready (BWRRDY)
  • DMA Interrupt (DMAINT)
  • Block Gap Event (BLKGE)
  • Transfer Complete (TRFC)

Only part of a command circuit is reset.

The following registers and bits are cleared by this bit:

• Present State Register :
  • Command Inhibit (CMD) (CMDINHC)
• Normal Interrupt Status Register :
  • Command Complete (CMDC)

This reset affects the entire peripheral except the card detection circuit. During initialization, the peripheral must be reset by setting this bit to 1. This bit is automatically cleared to 0 when SDHC_CA0R and SDHC_CA1R are valid and the user can read them. If this bit is set to 1, the user should issue a reset command and reinitialize the card.

List of registers cleared to 0:

• SDMA System Address / Argument 2 Register
• Block Size Register
• Block Count Register
• Argument 1 Register
• Transfer Mode Register
• Command Register
• Response Register n
• Buffer Data Port Register
• Present State Register (except CMDLL, DATLL, WRPPL, CARDDDPL, CARDSS, CARDINS)
• Host Control 1 Register
• Power Control Register
• Block Gap Control Register
• Wakeup Control Register
• Clock Control Register
• Timeout Control Register
• Normal Interrupt Status Register
• Error Interrupt Status Register
• Normal Interrupt Status Enable Register
• Error Interrupt Status Enable Register
• Normal Interrupt Signal Enable Register
• Error Interrupt Signal Enable Register
• Auto CMD Error Status Register
• Host Control 2 Register
• ADMA Error Status Register
• ADMA System Address Registers
• Slot Interrupt Status Register
• e.MMC Control 1 Register
• e.MMC Control 2 Register
• AHB Control Register
• Clock Control 2 Register
• Capabilities Control Register (except KEY)