40.8.18 SDHC Error Interrupt Status Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | EISTR |
| Offset: | 0x32 |
| Reset: | 0x0000 |
| Property: | - |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| BOOTAE | TUNING | ADMA | ACMD | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CURLIM | DATEND | DATCRC | DATTEO | CMDIDX | CMDEND | CMDCRC | CMDTEO | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 12 – BOOTAE Boot Acknowledge Error
This bit is set to 1 when detecting that the e.MMC Boot Acknowledge Status has a value other than “010”.
This bit can only be set to 1 if SDHC_EISTER.BOOTAE is set to 1. An interrupt can only be generated if SDHC_EISIER.BOOTAE is set to 1.
Writing this bit to 1 clears this bit.
| Value | Description |
|---|---|
| 0 |
No error |
| 1 |
Error |
Bit 10 – TUNING Tuning Error
This bit is set to 1 when an unrecoverable error is detected in a tuning circuit, except during a tuning procedure (occurrence of an error during tuning procedure is indicated by Sampling Clock Select (SCLKSEL) in SDHC_HC2R).
When detecting a tuning error, the user needs to abort the execution of a command and to perform tuning. To reset the tuning circuit, SCLKSEL must be set to 0 before executing the tuning procedure (refer to Figure 2-29 in the “SD Host Controller Simplified Specification V3.00” ).
Tuning Error has a higher priority than the other error statuses generated during data transfer. When detecting a tuning error, the user should discard any data transferred by a current read/write command and retry the transfer after the peripheral recovered from tuning circuit error.
This bit can only be set to 1 if SDHC_EISTER.TUNING is set to 1. An interrupt can only be generated if SDHC_EISIER. TUNING is set to 1.
Writing this bit to 1 clears this bit.
| Value | Description |
|---|---|
| 0 |
No error |
| 1 |
Error |
Bit 9 – ADMA ADMA Error
This bit is set to 1 when the peripheral detects errors during an ADMA-based data transfer. The state of the ADMA at an error occurrence is saved in SDHC_AESR.
In addition, the peripheral rises this status bit when it detects some invalid description data (Valid=0) at the ST_FDS state (refer to section “Advanced DMA” in the “SD Host Controller Simplified Specification V3.00”. ADMA Error Status (ERRST) in SDHC_AESR indicates that an error occurs in ST_FDS state. The user may find that the Valid bit is not set at the error descriptor.
This bit can only be set to 1 if SDHC_EISTER.ADMA is set to 1. An interrupt can only be generated if SDHC_EISIER.ADMA is set to 1.
Writing this bit to 1 clears this bit.
| Value | Description |
|---|---|
| 0 |
No error |
| 1 |
Error |
Bit 8 – ACMD Auto CMD Error
Auto CMD12 and Auto CMD23 use this error status. This bit is set to 1 when detecting that one of the 0 to 4 bits in SDHC_AESR (SDHC_ACESR[4:0]) has changed from 0 to 1. In the case of Auto CMD12, this bit is set to 1, not only when errors occur in Auto CMD12, but also when Auto CMD12 is not executed due to the previous command error.
This bit can only be set to 1 if SDHC_EISTER.ACMD is set to 1. An interrupt can only be generated if SDHC_EISIER.ACMD is set to 1.
Writing this bit to 1 clears this bit.
| Value | Description |
|---|---|
| 0 |
No error |
| 1 |
Error |
Bit 7 – CURLIM Current Limit Error
By setting SD Bus Power (SDBPWR) in SDHC_PCR, the peripheral is requested to supply power for the SD Bus. The peripheral is protected from an illegal card by stopping power supply to the card, in which case this bit indicates a failure status. Reading 1 means the peripheral is not supplying power to the card due to some failure. Reading 0 means that the peripheral is supplying power and no error has occurred. The peripheral may require some sampling time to detect the current limit.
This bit can only be set to 1 if SDHC_EISTER.CURLIM is set to 1. An interrupt can only be generated if SDHC_EISIER.CURLIM is set to 1.
Writing this bit to 1 clears this bit.
| Value | Description |
|---|---|
| 0 |
No error |
| 1 |
Error |
Bit 6 – DATEND Data End Bit Error
This bit is set to 1 either when detecting 0 at the end bit position of read data which uses the DAT line or at the end bit position of the CRC Status.
This bit can only be set to 1 if SDHC_EISTER.DATEND is set to 1. An interrupt can only be generated if SDHC_EISIER.DATEND is set to 1.
Writing this bit to 1 clears this bit.
| Value | Description |
|---|---|
| 0 |
No error |
| 1 |
Error |
Bit 5 – DATCRC Data CRC Error
This bit is set to 1 when detecting a CRC error during a transfer of read data which uses the DAT line or when detecting that the Write CRC Status has a value other than '010'.
This bit can only be set to 1 if SDHC_EISTER. DATCRC is set to 1. An interrupt can only be generated if SDHC_EISIER. DATCRC is set to 1.
Writing this bit to 1 clears this bit.
| Value | Description |
|---|---|
| 0 |
No error |
| 1 |
Error |
Bit 4 – DATTEO Data Timeout error
- Busy timeout for R1b, R5b response type (see “Physical Layer Simplified Specification V3.01” and “SDIO Simplified Specification V3.00” ).
- Busy timeout after Write CRC Status.
- Write CRC Status timeout.
- Read data timeout.
This bit can only be set to 1 if SDHC_EISTER.DATTEO is set to 1. An interrupt can only be generated if SDHC_EISIER.DATTEO is set to 1.
Writing this bit to 1 clears this bit.
| Value | Description |
|---|---|
| 0 |
No error |
| 1 |
Error |
Bit 3 – CMDIDX Command Index Error
This bit is set to 1 if a Command Index error occurs in the command response.
This bit can only be set to 1 if SDHC_EISTER.CMDIDX is set to 1. An interrupt can only be generated if SDHC_EISIER.CMDIDX is set to 1.
Writing this bit to 1 clears this bit.
| Value | Description |
|---|---|
| 0 |
No error |
| 1 |
Error |
Bit 2 – CMDEND Command End Bit Error
This bit is set to 1 when detecting that the end bit of a command response is 0.
This bit can only be set to 1 if SDHC_EISTER.CMDEND is set to 1. An interrupt can only be generated if SDHC_EISIER.CMDEND is set to 1.
Writing this bit to 1 clears this bit.
| Value | Description |
|---|---|
| 0 |
No error |
| 1 |
Error |
Bit 1 – CMDCRC Command CRC Error
The Command CRC Error is generated in two cases.
If a response is returned and Command Timeout Error (CMDTEO) is set to 0 (indicating no command timeout), this bit is set to 1 when detecting a CRC error in the command response.
The peripheral detects a CMD line conflict by monitoring the CMD line when a command is issued. If the peripheral drives the CMD line to 1 level, but detects 0 level on the CMD line at the next SDCLK edge, then the peripheral aborts the command (stops driving the CMD line) and sets this bit to 1. CMDTEO is also set to 1 to indicate a CMD line conflict.
This bit can only be set to 1 if SDHC_EISTER.CMDCRC is set to 1. An interrupt can only be generated if SDHC_EISIER.CMDCRC is set to 1.
Writing this bit to 1 clears this bit.
Bit 0 – CMDTEO Command Timeout Error
This bit is set to 1 only if no response is returned within 64 SDCLK cycles from the end bit of the command. If the peripheral detects a CMD line conflict, in which case Command CRC Error (CMDCRC) is also set to 1, this bit is set without waiting for 64 SDCLK cycles because the command is aborted by the peripheral.
This bit can only be set to 1 if SDHC_EISTER.CMDTEO is set to 1. An interrupt can only be generated if SDHC_EISIER.CMDTEO is set to 1.
Writing this bit to 1 clears this bit.
| CMDCRC | CMDTEO | Types of error |
|---|---|---|
| 0 | 0 | No error |
| 0 | 1 | Response timeout error |
| 1 | 0 | Response CRC error |
| 1 | 1 | CMD line conflict |