40.8.32 SDHC Preset Value Register

One of the Preset Value Registers is effective based on the selected bus speed mode. The table below defines the conditions to select one of the SDHC_PVRs.

Table 40-34. Preset Value Register Select Condition
Selected Bus Speed Mode	VS18EN (SDHC_HC2R)	HSEN (SDHC_HC1R)	UHSMS (SDHC_HC2R)
Default Speed	0	0	don’t care
High Speed	0	Response Timeout Error	don’t care
Reserved	1	don’t care	Other values

The following table shows the effective Preset Value Register according to the Selected Bus Speed mode.

Table 40-35. Preset Value Registers
SDHC_PVRx	Selected Bus Speed Mode	Signal Voltage
SDHC_PVR0	Initialization	3.3V or 1.8V
SDHC_PVR1	Default Speed	3.3V
SDHC_PVR2	High Speed	3.3V

When Preset Value Enable (PVALEN) in SDHC_HC2R is set to 1, SDCLK Frequency Select (SDLCKFSEL) and Clock Generator Select (CLKGSEL) in SDHC_CCR are automatically set based on the Selected Bus Speed mode. This means that the user does not need to set these fields when preset is enabled. A Preset Value Register for Initialization (SDHC_PVR0) is not selected by Bus Speed mode. Before starting the initialization sequence, the user needs to set a clock preset value to SDCLKFSEL in SDHC_CCR. PVALEN can be set to 1 after the initialization is completed.

Note: Preset Values in SDHC_PVRx registers are not supposed to be written by the user. However, the user can modify preset values only if Capabilities Write Enable (CAPWREN) is written to 1 in SDHC_CACR.

Table 40-36. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	PVRx
Offset:	0x60 + x*0x02 [x=0..7]
Reset:	0x0000
Property:	R/W


Bit	15	14	13	12	11	10	9	8
						CLKGSEL	SDCLKFSEL[9:8]
Access						R/W	R/W	R/W
Reset						0	0	0


Bit	7	6	5	4	3	2	1	0
	SDCLKFSEL[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 10 – CLKGSEL Clock Generator Select

Refer to CGGSEL in SDHC_CCR.

Bits 9:0 – SDCLKFSEL[9:0] SDCLK Frequency Select

Refer to SDCLKFSEL in SDHC_CCR.