40.8.29 SDHC Force Event Register for Error Interrupt Status

Table 40-31. Register Bit Attribute Legend
Symbol Description Symbol Description Symbol Description
R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented
W Writable bit HS Set by Hardware X Bit is unknown at Reset
K Write to clear S Software settable bit — —
Name: FEREIS
Offset: 0x52
Reset: 0x0000
Property: -

Bit 15141312111098 
    BOOTAE  ADMAACMD 
Access WWW 
Reset 000 
Bit 76543210 
 CURLIMDATENDDATCRCDATTEOCMDIDXCMDENDCMDCRCCMDTEO 
Access WWWWWWWW 
Reset 00000000 

Bit 12 – BOOTAE Force Event for Boot Acknowledge Error

For testing purposes, the user can write this bit to 1 to rise the BOOTAE status flag in SDHC_EISTR.

Writing this bit to 0 has no effect.

Bit 9 – ADMA Force Event for ADMA Error

For testing purposes, the user can write this bit to 1 to rise the ADMA status flag in SDHC_EISTR.

Writing this bit to 0 has no effect.

Bit 8 – ACMD Force Event for Auto CMD Error

For testing purposes, the user can write this bit to 1 to rise the ACMD status flag in SDHC_EISTR.

Writing this bit to 0 has no effect.

Bit 7 – CURLIM Force Event for Current Limit Error

For testing purposes, the user can write this bit to 1 to rise the CURLIM status flag in SDHC_EISTR.

Writing this bit to 0 has no effect.

Bit 6 – DATEND Force Event for Data End Bit Error

For testing purposes, the user can write this bit to 1 to rise the DATEND status flag in SDHC_EISTR.

Writing this bit to 0 has no effect.

Bit 5 – DATCRC Force Event for Data CRC error

For testing purposes, the user can write this bit to 1 to rise the DATCRC status flag in SDHC_EISTR.

Writing this bit to 0 has no effect.

Bit 4 – DATTEO Force Event for Data Timeout error

For testing purposes, the user can write this bit to 1 to rise the DATTEO status flag in SDHC_EISTR.

Writing this bit to 0 has no effect.

Bit 3 – CMDIDX Force Event for Command Index Error

For testing purposes, the user can write this bit to 1 to rise the CMDIDX status flag in SDHC_EISTR.

Writing this bit to 0 has no effect.

Bit 2 – CMDEND Force Event for Command End Bit Error

For testing purposes, the user can write this bit to 1 to rise the CDMEND status flag in SDHC_EISTR.

Writing this bit to 0 has no effect.

Bit 1 – CMDCRC Force Event for Command CRC Error

For testing purposes, the user can write this bit to 1 to rise the CMDCRC status flag in SDHC_EISTR.

Writing this bit to 0 has no effect.

Bit 0 – CMDTEO Force Event for Command Timeout Error

For testing purposes, the user can write this bit to 1 to rise the CMDTEO status flag in SDHC_EISTR.

Writing this bit to 0 has no effect.