40.8.25 SDHC Capabilities 0 Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CA0R |
| Offset: | 0x40 |
| Reset: | 0x27E80080 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| SLTYPE[1:0] | ASINTSUP | SB64SUP | V30VSUP | V33VSUP | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 1 | 0 | 1 | 1 | |||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SRSUP | SDMASUP | HSSUP | ADMA2SUP | ED8SUP | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 1 | 1 | 1 | 1 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| BASECLKF[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TEOCLKU | TEOCLKF[5:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 1 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bits 31:30 – SLTYPE[1:0] Slot Type
This field indicates usage of a slot by a specific system. An peripheral control register set is defined per slot.
Embedded Slot for One Device means that only one non-removable device is connected to a bus slot.
The Standard Host Driver controls a removable card (SLTYPE = 0) or one embedded device (SLTYPE = 1) connected to an SD bus slot.
| Value | Name |
|---|---|
| 0 | Removable Card Slot |
| 1 | Embedded Slot for One Device |
| 2 | Shared Bus Slot |
| 2 | Reserved |
| 3 | Reserved |
Bit 29 – ASINTSUP Asynchronous Interrupt Support
Refer to section “Asynchronous Interrupt” in the “SDIO Simplified Specification V3.00”.
| Value | Description |
|---|---|
| 0 |
Asynchronous interrupt not supported |
| 1 |
Asynchronous interrupt supported |
Bit 28 – SB64SUP 64-Bit System Bus Support
This bit indicates if the peripheral supports the 64-bit Address Descriptor mode and is connected to the 64-bit address system bus.
| Value | Description |
|---|---|
| 0 |
64-bit address bus not supported |
| 1 |
64-bit address bus supported |
Bit 25 – V30VSUP Voltage Support 3.0V
| Value | Description |
|---|---|
| 0 |
3.0V Voltage supply not supported |
| 1 |
3.0V Voltage supply supported |
Bit 24 – V33VSUP Voltage Support 3.3V
| Value | Description |
|---|---|
| 0 |
3.3V Voltage supply not supported |
| 1 |
3.3V Voltage supply supported |
Bit 23 – SRSUP Suspend/Resume Support
This bit indicates whether the peripheral supports the Suspend/Resume functionality. If this bit is set to 0, the user does not issue either Suspend or Resume commands because the Suspend and Resume mechanism (refer to “Suspend and Resume Mechanism” in the “SD Host Controller Simplified Specification V3.00” ) is not supported.
| Value | Description |
|---|---|
| 0 |
Suspend/Resume not supported |
| 1 |
Suspend/Resume supported |
Bit 22 – SDMASUP SDMA Support
This bit indicates whether the peripheral is capable of using SDMA to transfer data between system memory and the peripheral directly.
| Value | Description |
|---|---|
| 0 |
SDMA not supported |
| 1 |
SDMA supported |
Bit 21 – HSSUP High Speed Support
This bit indicates whether the peripheral and the system support High Speed mode and they can supply SDCLK frequency from 25MHz to 50MHz.
| Value | Description |
|---|---|
| 0 |
High Speed not supported |
| 1 |
High Speed supported |
Bit 19 – ADMA2SUP ADMA2 Support
This bit indicates whether the peripheral is capable of using ADMA2.
| Value | Description |
|---|---|
| 0 |
ADMA2 not supported |
| 1 |
ADMA2 supported |
Bit 18 – ED8SUP 8-Bit Support for Embedded Device
This bit indicates whether the peripheral is capable of using the 8-bit Bus Width mode.
| Value | Description |
|---|---|
| 0 |
8-bit bus width not supported |
| 1 |
8-bit bus width supported |
Bits 15:8 – BASECLKF[7:0] Base Clock Frequency
This value indicates the frequency of the base clock (BASECLK). The user uses this value to calculate the clock divider value (refer to SDCLK Frequency Select (SDCLKFSEL) in SDHC_CCR).
If this field is set to 0, the user must get the information via another method.
Bit 7 – TEOCLKU Timeout Clock Unit
This bit shows the unit of the base clock frequency used to detect Data Timeout Error.
| Value | Description |
|---|---|
| 0 |
kHz |
| 1 |
MHz |
Bits 5:0 – TEOCLKF[5:0] Timeout Clock Frequency
This bit shows the timeout clock frequency (TEOCLK) used to detect Data Timeout Error.
If this field is set to 0, the user must get the information via another method.
The Timeout Clock Unit (TEOCLKU) defines the unit of this field’s value.
– TEOCLKU = 0:
– TEOCLKU = 1: